2 * QEMU Sun4m System Emulator
4 * Copyright (c) 2003-2004 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
27 #define KERNEL_LOAD_ADDR 0x00004000
28 #define MMU_CONTEXT_TBL 0x00003000
29 #define MMU_L1PTP (MMU_CONTEXT_TBL + 0x0400)
30 #define MMU_L2PTP (MMU_CONTEXT_TBL + 0x0800)
31 #define PROM_ADDR 0xffd04000
32 #define PROM_FILENAMEB "proll.bin"
33 #define PROM_FILENAMEE "proll.elf"
34 #define PROLL_MAGIC_ADDR 0x20000000
35 #define PHYS_JJ_EEPROM 0x71200000 /* [2000] MK48T08 */
36 #define PHYS_JJ_IDPROM_OFF 0x1FD8
37 #define PHYS_JJ_EEPROM_SIZE 0x2000
38 #define PHYS_JJ_IOMMU 0x10000000 /* First page of sun4m IOMMU */
39 #define PHYS_JJ_TCX_FB 0x50800000 /* Start address, frame buffer body */
40 #define PHYS_JJ_TCX_0E 0x5E000000 /* Top address, one byte used. */
41 #define PHYS_JJ_IOMMU 0x10000000 /* First page of sun4m IOMMU */
42 #define PHYS_JJ_LEDMA 0x78400010 /* ledma, off by 10 from unused SCSI */
43 #define PHYS_JJ_LE 0x78C00000 /* LANCE, typical sun4m */
44 #define PHYS_JJ_LE_IRQ 6
45 #define PHYS_JJ_CLOCK 0x71D00000
46 #define PHYS_JJ_CLOCK_IRQ 10
47 #define PHYS_JJ_CLOCK1 0x71D10000
48 #define PHYS_JJ_CLOCK1_IRQ 14
49 #define PHYS_JJ_INTR0 0x71E00000 /* CPU0 interrupt control registers */
50 #define PHYS_JJ_INTR_G 0x71E10000 /* Master interrupt control registers */
54 uint64_t cpu_get_tsc()
56 return qemu_get_clock(vm_clock);
61 int serial_can_receive(SerialState *s) { return 0; }
62 void serial_receive_byte(SerialState *s, int ch) {}
63 void serial_receive_break(SerialState *s) {}
65 static m48t08_t *nvram;
67 /* Sun4m hardware initialisation */
68 void sun4m_init(int ram_size, int vga_ram_size, int boot_device,
69 DisplayState *ds, const char **fd_filename, int snapshot,
70 const char *kernel_filename, const char *kernel_cmdline,
71 const char *initrd_filename)
75 unsigned long bios_offset;
77 linux_boot = (kernel_filename != NULL);
80 cpu_register_physical_memory(0, ram_size, 0);
81 bios_offset = ram_size;
83 iommu_init(PHYS_JJ_IOMMU);
84 sched_init(PHYS_JJ_INTR0, PHYS_JJ_INTR_G);
85 tcx_init(ds, PHYS_JJ_TCX_FB);
86 lance_init(&nd_table[0], PHYS_JJ_LE_IRQ, PHYS_JJ_LE, PHYS_JJ_LEDMA);
87 nvram = m48t08_init(PHYS_JJ_EEPROM, PHYS_JJ_EEPROM_SIZE, &nd_table[0].macaddr);
88 timer_init(PHYS_JJ_CLOCK, PHYS_JJ_CLOCK_IRQ);
89 timer_init(PHYS_JJ_CLOCK1, PHYS_JJ_CLOCK1_IRQ);
90 magic_init(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR, PROLL_MAGIC_ADDR);
92 /* We load Proll as the kernel and start it. It will issue a magic
93 IO to load the real kernel */
95 snprintf(buf, sizeof(buf), "%s/%s", bios_dir, PROM_FILENAMEB);
96 ret = load_kernel(buf,
97 phys_ram_base + KERNEL_LOAD_ADDR);
99 fprintf(stderr, "qemu: could not load kernel '%s'\n",
104 /* Setup a MMU entry for entire address space */
105 stl_raw(phys_ram_base + MMU_CONTEXT_TBL, (MMU_L1PTP >> 4) | 1);
106 stl_raw(phys_ram_base + MMU_L1PTP, (MMU_L2PTP >> 4) | 1);
107 stl_raw(phys_ram_base + MMU_L1PTP + (0x01 << 2), (MMU_L2PTP >> 4) | 1); // 01.. == 00..
108 stl_raw(phys_ram_base + MMU_L1PTP + (0xff << 2), (MMU_L2PTP >> 4) | 1); // ff.. == 00..
109 stl_raw(phys_ram_base + MMU_L1PTP + (0xf0 << 2), (MMU_L2PTP >> 4) | 1); // f0.. == 00..
110 /* 3 = U:RWX S:RWX */
111 stl_raw(phys_ram_base + MMU_L2PTP, (3 << PTE_ACCESS_SHIFT) | 2);
112 stl_raw(phys_ram_base + MMU_L2PTP, ((0x01 << PTE_PPN_SHIFT) >> 4 ) | (3 << PTE_ACCESS_SHIFT) | 2);