2 * QEMU Sun4m System Emulator
4 * Copyright (c) 2003-2005 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 #define KERNEL_LOAD_ADDR 0x00004000
27 #define CMDLINE_ADDR 0x007ff000
28 #define INITRD_LOAD_ADDR 0x00800000
29 #define PROM_SIZE_MAX (256 * 1024)
30 #define PROM_ADDR 0xffd00000
31 #define PROM_FILENAME "openbios-sparc32"
32 #define PHYS_JJ_EEPROM 0x71200000 /* m48t08 */
33 #define PHYS_JJ_IDPROM_OFF 0x1FD8
34 #define PHYS_JJ_EEPROM_SIZE 0x2000
35 // IRQs are not PIL ones, but master interrupt controller register
37 #define PHYS_JJ_IOMMU 0x10000000 /* I/O MMU */
38 #define PHYS_JJ_TCX_FB 0x50000000 /* TCX frame buffer */
39 #define PHYS_JJ_SLAVIO 0x70000000 /* Slavio base */
40 #define PHYS_JJ_DMA 0x78400000 /* DMA controller */
41 #define PHYS_JJ_ESP 0x78800000 /* ESP SCSI */
42 #define PHYS_JJ_ESP_IRQ 18
43 #define PHYS_JJ_LE 0x78C00000 /* Lance ethernet */
44 #define PHYS_JJ_LE_IRQ 16
45 #define PHYS_JJ_CLOCK 0x71D00000 /* Per-CPU timer/counter, L14 */
46 #define PHYS_JJ_CLOCK_IRQ 7
47 #define PHYS_JJ_CLOCK1 0x71D10000 /* System timer/counter, L10 */
48 #define PHYS_JJ_CLOCK1_IRQ 19
49 #define PHYS_JJ_INTR0 0x71E00000 /* Per-CPU interrupt control registers */
50 #define PHYS_JJ_INTR_G 0x71E10000 /* Master interrupt control registers */
51 #define PHYS_JJ_MS_KBD 0x71000000 /* Mouse and keyboard */
52 #define PHYS_JJ_MS_KBD_IRQ 14
53 #define PHYS_JJ_SER 0x71100000 /* Serial */
54 #define PHYS_JJ_SER_IRQ 15
55 #define PHYS_JJ_FDC 0x71400000 /* Floppy */
56 #define PHYS_JJ_FLOPPY_IRQ 22
57 #define PHYS_JJ_ME_IRQ 30 /* Module error, power fail */
62 uint64_t cpu_get_tsc()
64 return qemu_get_clock(vm_clock);
67 int DMA_get_channel_mode (int nchan)
71 int DMA_read_memory (int nchan, void *buf, int pos, int size)
75 int DMA_write_memory (int nchan, void *buf, int pos, int size)
79 void DMA_hold_DREQ (int nchan) {}
80 void DMA_release_DREQ (int nchan) {}
81 void DMA_schedule(int nchan) {}
82 void DMA_run (void) {}
83 void DMA_init (int high_page_enable) {}
84 void DMA_register_channel (int nchan,
85 DMA_transfer_handler transfer_handler,
90 static void nvram_set_word (m48t59_t *nvram, uint32_t addr, uint16_t value)
92 m48t59_write(nvram, addr++, (value >> 8) & 0xff);
93 m48t59_write(nvram, addr++, value & 0xff);
96 static void nvram_set_lword (m48t59_t *nvram, uint32_t addr, uint32_t value)
98 m48t59_write(nvram, addr++, value >> 24);
99 m48t59_write(nvram, addr++, (value >> 16) & 0xff);
100 m48t59_write(nvram, addr++, (value >> 8) & 0xff);
101 m48t59_write(nvram, addr++, value & 0xff);
104 static void nvram_set_string (m48t59_t *nvram, uint32_t addr,
105 const unsigned char *str, uint32_t max)
109 for (i = 0; i < max && str[i] != '\0'; i++) {
110 m48t59_write(nvram, addr + i, str[i]);
112 m48t59_write(nvram, addr + max - 1, '\0');
115 static m48t59_t *nvram;
117 extern int nographic;
119 static void nvram_init(m48t59_t *nvram, uint8_t *macaddr, const char *cmdline,
120 int boot_device, uint32_t RAM_size,
121 uint32_t kernel_size,
122 int width, int height, int depth)
124 unsigned char tmp = 0;
127 // Try to match PPC NVRAM
128 nvram_set_string(nvram, 0x00, "QEMU_BIOS", 16);
129 nvram_set_lword(nvram, 0x10, 0x00000001); /* structure v1 */
130 // NVRAM_size, arch not applicable
131 m48t59_write(nvram, 0x2D, smp_cpus & 0xff);
132 m48t59_write(nvram, 0x2E, 0);
133 m48t59_write(nvram, 0x2F, nographic & 0xff);
134 nvram_set_lword(nvram, 0x30, RAM_size);
135 m48t59_write(nvram, 0x34, boot_device & 0xff);
136 nvram_set_lword(nvram, 0x38, KERNEL_LOAD_ADDR);
137 nvram_set_lword(nvram, 0x3C, kernel_size);
139 strcpy(phys_ram_base + CMDLINE_ADDR, cmdline);
140 nvram_set_lword(nvram, 0x40, CMDLINE_ADDR);
141 nvram_set_lword(nvram, 0x44, strlen(cmdline));
143 // initrd_image, initrd_size passed differently
144 nvram_set_word(nvram, 0x54, width);
145 nvram_set_word(nvram, 0x56, height);
146 nvram_set_word(nvram, 0x58, depth);
148 // Sun4m specific use
150 m48t59_write(nvram, i++, 0x01);
151 m48t59_write(nvram, i++, 0x80); /* Sun4m OBP */
153 m48t59_write(nvram, i++, macaddr[j++]);
154 m48t59_write(nvram, i++, macaddr[j++]);
155 m48t59_write(nvram, i++, macaddr[j++]);
156 m48t59_write(nvram, i++, macaddr[j++]);
157 m48t59_write(nvram, i++, macaddr[j++]);
158 m48t59_write(nvram, i, macaddr[j]);
160 /* Calculate checksum */
161 for (i = 0x1fd8; i < 0x1fe7; i++) {
162 tmp ^= m48t59_read(nvram, i);
164 m48t59_write(nvram, 0x1fe7, tmp);
167 static void *slavio_intctl;
171 slavio_pic_info(slavio_intctl);
176 slavio_irq_info(slavio_intctl);
179 void pic_set_irq(int irq, int level)
181 slavio_pic_set_irq(slavio_intctl, irq, level);
184 void pic_set_irq_new(void *opaque, int irq, int level)
186 pic_set_irq(irq, level);
189 void pic_set_irq_cpu(int irq, int level, unsigned int cpu)
191 slavio_pic_set_irq_cpu(slavio_intctl, irq, level, cpu);
194 static void *slavio_misc;
196 void qemu_system_powerdown(void)
198 slavio_set_power_fail(slavio_misc, 1);
201 static void main_cpu_reset(void *opaque)
203 CPUState *env = opaque;
207 /* Sun4m hardware initialisation */
208 static void sun4m_init(int ram_size, int vga_ram_size, int boot_device,
209 DisplayState *ds, const char **fd_filename, int snapshot,
210 const char *kernel_filename, const char *kernel_cmdline,
211 const char *initrd_filename)
213 CPUState *env, *envs[MAX_CPUS];
217 long vram_size = 0x100000, prom_offset, initrd_size, kernel_size;
218 void *iommu, *dma, *main_esp, *main_lance = NULL;
220 linux_boot = (kernel_filename != NULL);
223 for(i = 0; i < smp_cpus; i++) {
228 register_savevm("cpu", i, 3, cpu_save, cpu_load, env);
229 qemu_register_reset(main_cpu_reset, env);
232 cpu_register_physical_memory(0, ram_size, 0);
234 iommu = iommu_init(PHYS_JJ_IOMMU);
235 slavio_intctl = slavio_intctl_init(PHYS_JJ_INTR0, PHYS_JJ_INTR_G);
236 for(i = 0; i < smp_cpus; i++) {
237 slavio_intctl_set_cpu(slavio_intctl, i, envs[i]);
239 dma = sparc32_dma_init(PHYS_JJ_DMA, PHYS_JJ_ESP_IRQ, PHYS_JJ_LE_IRQ, iommu, slavio_intctl);
241 tcx_init(ds, PHYS_JJ_TCX_FB, phys_ram_base + ram_size, ram_size, vram_size, graphic_width, graphic_height);
242 if (nd_table[0].vlan) {
243 if (nd_table[0].model == NULL
244 || strcmp(nd_table[0].model, "lance") == 0) {
245 main_lance = lance_init(&nd_table[0], PHYS_JJ_LE, dma);
247 fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model);
251 nvram = m48t59_init(0, PHYS_JJ_EEPROM, 0, PHYS_JJ_EEPROM_SIZE, 8);
252 for (i = 0; i < MAX_CPUS; i++) {
253 slavio_timer_init(PHYS_JJ_CLOCK + i * TARGET_PAGE_SIZE, PHYS_JJ_CLOCK_IRQ, 0, i);
255 slavio_timer_init(PHYS_JJ_CLOCK1, PHYS_JJ_CLOCK1_IRQ, 2, (unsigned int)-1);
256 slavio_serial_ms_kbd_init(PHYS_JJ_MS_KBD, PHYS_JJ_MS_KBD_IRQ);
257 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
258 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
259 slavio_serial_init(PHYS_JJ_SER, PHYS_JJ_SER_IRQ, serial_hds[1], serial_hds[0]);
260 fdctrl_init(PHYS_JJ_FLOPPY_IRQ, 0, 1, PHYS_JJ_FDC, fd_table);
261 main_esp = esp_init(bs_table, PHYS_JJ_ESP, dma);
262 slavio_misc = slavio_misc_init(PHYS_JJ_SLAVIO, PHYS_JJ_ME_IRQ);
263 sparc32_dma_set_reset_data(dma, main_esp, main_lance);
265 prom_offset = ram_size + vram_size;
266 cpu_register_physical_memory(PROM_ADDR,
267 (PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK,
268 prom_offset | IO_MEM_ROM);
270 snprintf(buf, sizeof(buf), "%s/%s", bios_dir, PROM_FILENAME);
271 ret = load_elf(buf, 0, NULL);
273 fprintf(stderr, "qemu: could not load prom '%s'\n",
280 kernel_size = load_elf(kernel_filename, -0xf0000000, NULL);
282 kernel_size = load_aout(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR);
284 kernel_size = load_image(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR);
285 if (kernel_size < 0) {
286 fprintf(stderr, "qemu: could not load kernel '%s'\n",
293 if (initrd_filename) {
294 initrd_size = load_image(initrd_filename, phys_ram_base + INITRD_LOAD_ADDR);
295 if (initrd_size < 0) {
296 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
301 if (initrd_size > 0) {
302 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
303 if (ldl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i)
304 == 0x48647253) { // HdrS
305 stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR);
306 stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 20, initrd_size);
312 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline, boot_device, ram_size, kernel_size, graphic_width, graphic_height, graphic_depth);
315 QEMUMachine sun4m_machine = {