2 * QEMU Sun4m System Emulator
4 * Copyright (c) 2003-2005 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
27 * Sun4m architecture was used in the following machines:
29 * SPARCserver 6xxMP/xx
30 * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15), SPARCclassic X (4/10)
31 * SPARCstation LX/ZX (4/30)
32 * SPARCstation Voyager
33 * SPARCstation 10/xx, SPARCserver 10/xx
34 * SPARCstation 5, SPARCserver 5
35 * SPARCstation 20/xx, SPARCserver 20
38 * See for example: http://www.sunhelp.org/faq/sunref1.html
41 #define KERNEL_LOAD_ADDR 0x00004000
42 #define CMDLINE_ADDR 0x007ff000
43 #define INITRD_LOAD_ADDR 0x00800000
44 #define PROM_SIZE_MAX (256 * 1024)
45 #define PROM_ADDR 0xffd00000
46 #define PROM_FILENAME "openbios-sparc32"
51 target_phys_addr_t iommu_base, slavio_base;
52 target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base;
53 target_phys_addr_t serial_base, fd_base;
54 target_phys_addr_t dma_base, esp_base, le_base;
55 target_phys_addr_t tcx_base, cs_base, power_base;
56 long vram_size, nvram_size;
57 // IRQ numbers are not PIL ones, but master interrupt controller register
59 int intctl_g_intr, esp_irq, le_irq, clock_irq, clock1_irq;
60 int ser_irq, ms_kb_irq, fd_irq, me_irq, cs_irq;
61 int machine_id; // For NVRAM
62 uint32_t intbit_to_level[32];
67 uint64_t cpu_get_tsc()
69 return qemu_get_clock(vm_clock);
72 int DMA_get_channel_mode (int nchan)
76 int DMA_read_memory (int nchan, void *buf, int pos, int size)
80 int DMA_write_memory (int nchan, void *buf, int pos, int size)
84 void DMA_hold_DREQ (int nchan) {}
85 void DMA_release_DREQ (int nchan) {}
86 void DMA_schedule(int nchan) {}
87 void DMA_run (void) {}
88 void DMA_init (int high_page_enable) {}
89 void DMA_register_channel (int nchan,
90 DMA_transfer_handler transfer_handler,
95 static void nvram_set_word (m48t59_t *nvram, uint32_t addr, uint16_t value)
97 m48t59_write(nvram, addr++, (value >> 8) & 0xff);
98 m48t59_write(nvram, addr++, value & 0xff);
101 static void nvram_set_lword (m48t59_t *nvram, uint32_t addr, uint32_t value)
103 m48t59_write(nvram, addr++, value >> 24);
104 m48t59_write(nvram, addr++, (value >> 16) & 0xff);
105 m48t59_write(nvram, addr++, (value >> 8) & 0xff);
106 m48t59_write(nvram, addr++, value & 0xff);
109 static void nvram_set_string (m48t59_t *nvram, uint32_t addr,
110 const unsigned char *str, uint32_t max)
114 for (i = 0; i < max && str[i] != '\0'; i++) {
115 m48t59_write(nvram, addr + i, str[i]);
117 m48t59_write(nvram, addr + max - 1, '\0');
120 static uint32_t nvram_set_var (m48t59_t *nvram, uint32_t addr,
121 const unsigned char *str)
125 len = strlen(str) + 1;
126 nvram_set_string(nvram, addr, str, len);
131 static void nvram_finish_partition (m48t59_t *nvram, uint32_t start,
136 // Length divided by 16
137 m48t59_write(nvram, start + 2, ((end - start) >> 12) & 0xff);
138 m48t59_write(nvram, start + 3, ((end - start) >> 4) & 0xff);
140 sum = m48t59_read(nvram, start);
141 for (i = 0; i < 14; i++) {
142 sum += m48t59_read(nvram, start + 2 + i);
143 sum = (sum + ((sum & 0xff00) >> 8)) & 0xff;
145 m48t59_write(nvram, start + 1, sum & 0xff);
148 static m48t59_t *nvram;
150 extern int nographic;
152 static void nvram_init(m48t59_t *nvram, uint8_t *macaddr, const char *cmdline,
153 int boot_device, uint32_t RAM_size,
154 uint32_t kernel_size,
155 int width, int height, int depth,
158 unsigned char tmp = 0;
162 // Try to match PPC NVRAM
163 nvram_set_string(nvram, 0x00, "QEMU_BIOS", 16);
164 nvram_set_lword(nvram, 0x10, 0x00000001); /* structure v1 */
165 // NVRAM_size, arch not applicable
166 m48t59_write(nvram, 0x2D, smp_cpus & 0xff);
167 m48t59_write(nvram, 0x2E, 0);
168 m48t59_write(nvram, 0x2F, nographic & 0xff);
169 nvram_set_lword(nvram, 0x30, RAM_size);
170 m48t59_write(nvram, 0x34, boot_device & 0xff);
171 nvram_set_lword(nvram, 0x38, KERNEL_LOAD_ADDR);
172 nvram_set_lword(nvram, 0x3C, kernel_size);
174 strcpy(phys_ram_base + CMDLINE_ADDR, cmdline);
175 nvram_set_lword(nvram, 0x40, CMDLINE_ADDR);
176 nvram_set_lword(nvram, 0x44, strlen(cmdline));
178 // initrd_image, initrd_size passed differently
179 nvram_set_word(nvram, 0x54, width);
180 nvram_set_word(nvram, 0x56, height);
181 nvram_set_word(nvram, 0x58, depth);
183 // OpenBIOS nvram variables
184 // Variable partition
186 m48t59_write(nvram, start, 0x70);
187 nvram_set_string(nvram, start + 4, "system", 12);
190 for (i = 0; i < nb_prom_envs; i++)
191 end = nvram_set_var(nvram, end, prom_envs[i]);
193 m48t59_write(nvram, end++ , 0);
194 end = start + ((end - start + 15) & ~15);
195 nvram_finish_partition(nvram, start, end);
199 m48t59_write(nvram, start, 0x7f);
200 nvram_set_string(nvram, start + 4, "free", 12);
203 nvram_finish_partition(nvram, start, end);
205 // Sun4m specific use
207 m48t59_write(nvram, i++, 0x01);
208 m48t59_write(nvram, i++, machine_id);
210 m48t59_write(nvram, i++, macaddr[j++]);
211 m48t59_write(nvram, i++, macaddr[j++]);
212 m48t59_write(nvram, i++, macaddr[j++]);
213 m48t59_write(nvram, i++, macaddr[j++]);
214 m48t59_write(nvram, i++, macaddr[j++]);
215 m48t59_write(nvram, i, macaddr[j]);
217 /* Calculate checksum */
218 for (i = start; i < start + 15; i++) {
219 tmp ^= m48t59_read(nvram, i);
221 m48t59_write(nvram, start + 15, tmp);
224 static void *slavio_intctl;
228 slavio_pic_info(slavio_intctl);
233 slavio_irq_info(slavio_intctl);
236 static void *slavio_misc;
238 void qemu_system_powerdown(void)
240 slavio_set_power_fail(slavio_misc, 1);
243 static void main_cpu_reset(void *opaque)
245 CPUState *env = opaque;
251 static void secondary_cpu_reset(void *opaque)
253 CPUState *env = opaque;
259 static void sun4m_hw_init(const struct hwdef *hwdef, int ram_size,
260 DisplayState *ds, const char *cpu_model)
263 CPUState *env, *envs[MAX_CPUS];
265 void *iommu, *espdma, *ledma, *main_esp;
266 const sparc_def_t *def;
267 qemu_irq *slavio_irq, *slavio_cpu_irq,
268 *espdma_irq, *ledma_irq;
271 sparc_find_by_name(cpu_model, &def);
273 fprintf(stderr, "Unable to find Sparc CPU definition\n");
276 for(i = 0; i < smp_cpus; i++) {
278 cpu_sparc_register(env, def);
281 qemu_register_reset(main_cpu_reset, env);
283 qemu_register_reset(secondary_cpu_reset, env);
286 register_savevm("cpu", i, 3, cpu_save, cpu_load, env);
289 cpu_register_physical_memory(0, ram_size, 0);
291 iommu = iommu_init(hwdef->iommu_base);
292 slavio_intctl = slavio_intctl_init(hwdef->intctl_base,
293 hwdef->intctl_base + 0x10000ULL,
294 &hwdef->intbit_to_level[0],
295 &slavio_irq, &slavio_cpu_irq,
297 for(i = 0; i < smp_cpus; i++) {
298 slavio_intctl_set_cpu(slavio_intctl, i, envs[i]);
300 espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[hwdef->esp_irq],
302 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
303 slavio_irq[hwdef->le_irq], iommu, &ledma_irq);
305 if (graphic_depth != 8 && graphic_depth != 24) {
306 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
309 tcx_init(ds, hwdef->tcx_base, phys_ram_base + ram_size, ram_size,
310 hwdef->vram_size, graphic_width, graphic_height, graphic_depth);
311 if (nd_table[0].vlan) {
312 if (nd_table[0].model == NULL
313 || strcmp(nd_table[0].model, "lance") == 0) {
314 lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq);
316 fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model);
320 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0,
321 hwdef->nvram_size, 8);
322 for (i = 0; i < MAX_CPUS; i++) {
323 slavio_timer_init(hwdef->counter_base +
324 (target_phys_addr_t)(i * TARGET_PAGE_SIZE),
325 slavio_cpu_irq[i], 0);
327 slavio_timer_init(hwdef->counter_base + 0x10000ULL,
328 slavio_irq[hwdef->clock1_irq], 2);
329 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[hwdef->ms_kb_irq]);
330 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
331 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
332 slavio_serial_init(hwdef->serial_base, slavio_irq[hwdef->ser_irq],
333 serial_hds[1], serial_hds[0]);
334 fdctrl_init(slavio_irq[hwdef->fd_irq], 0, 1, hwdef->fd_base, fd_table);
335 main_esp = esp_init(bs_table, hwdef->esp_base, espdma, *espdma_irq);
337 for (i = 0; i < MAX_DISKS; i++) {
339 esp_scsi_attach(main_esp, bs_table[i], i);
343 slavio_misc = slavio_misc_init(hwdef->slavio_base, hwdef->power_base,
344 slavio_irq[hwdef->me_irq]);
345 if (hwdef->cs_base != (target_phys_addr_t)-1)
346 cs_init(hwdef->cs_base, hwdef->cs_irq, slavio_intctl);
349 static void sun4m_load_kernel(long vram_size, int ram_size, int boot_device,
350 const char *kernel_filename,
351 const char *kernel_cmdline,
352 const char *initrd_filename,
358 long prom_offset, initrd_size, kernel_size;
360 linux_boot = (kernel_filename != NULL);
362 prom_offset = ram_size + vram_size;
363 cpu_register_physical_memory(PROM_ADDR,
364 (PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK,
365 prom_offset | IO_MEM_ROM);
367 snprintf(buf, sizeof(buf), "%s/%s", bios_dir, PROM_FILENAME);
368 ret = load_elf(buf, 0, NULL, NULL, NULL);
370 fprintf(stderr, "qemu: could not load prom '%s'\n",
377 kernel_size = load_elf(kernel_filename, -0xf0000000, NULL, NULL, NULL);
379 kernel_size = load_aout(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR);
381 kernel_size = load_image(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR);
382 if (kernel_size < 0) {
383 fprintf(stderr, "qemu: could not load kernel '%s'\n",
390 if (initrd_filename) {
391 initrd_size = load_image(initrd_filename, phys_ram_base + INITRD_LOAD_ADDR);
392 if (initrd_size < 0) {
393 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
398 if (initrd_size > 0) {
399 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
400 if (ldl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i)
401 == 0x48647253) { // HdrS
402 stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR);
403 stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 20, initrd_size);
409 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
410 boot_device, ram_size, kernel_size, graphic_width,
411 graphic_height, graphic_depth, machine_id);
414 static const struct hwdef hwdefs[] = {
417 .iommu_base = 0x10000000,
418 .tcx_base = 0x50000000,
419 .cs_base = 0x6c000000,
420 .slavio_base = 0x70000000,
421 .ms_kb_base = 0x71000000,
422 .serial_base = 0x71100000,
423 .nvram_base = 0x71200000,
424 .fd_base = 0x71400000,
425 .counter_base = 0x71d00000,
426 .intctl_base = 0x71e00000,
427 .dma_base = 0x78400000,
428 .esp_base = 0x78800000,
429 .le_base = 0x78c00000,
430 .power_base = 0x7a000000,
431 .vram_size = 0x00100000,
432 .nvram_size = 0x2000,
444 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
445 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
450 .iommu_base = 0xfe0000000ULL,
451 .tcx_base = 0xe20000000ULL,
453 .slavio_base = 0xff0000000ULL,
454 .ms_kb_base = 0xff1000000ULL,
455 .serial_base = 0xff1100000ULL,
456 .nvram_base = 0xff1200000ULL,
457 .fd_base = 0xff1700000ULL,
458 .counter_base = 0xff1300000ULL,
459 .intctl_base = 0xff1400000ULL,
460 .dma_base = 0xef0400000ULL,
461 .esp_base = 0xef0800000ULL,
462 .le_base = 0xef0c00000ULL,
463 .power_base = 0xefa000000ULL,
464 .vram_size = 0x00100000,
465 .nvram_size = 0x2000,
477 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
478 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
483 static void sun4m_common_init(int ram_size, int boot_device, DisplayState *ds,
484 const char *kernel_filename, const char *kernel_cmdline,
485 const char *initrd_filename, const char *cpu_model,
486 unsigned int machine, int max_ram)
488 if ((unsigned int)ram_size > (unsigned int)max_ram) {
489 fprintf(stderr, "qemu: Too much memory for this machine: %d, maximum %d\n",
490 (unsigned int)ram_size / (1024 * 1024),
491 (unsigned int)max_ram / (1024 * 1024));
494 sun4m_hw_init(&hwdefs[machine], ram_size, ds, cpu_model);
496 sun4m_load_kernel(hwdefs[machine].vram_size, ram_size, boot_device,
497 kernel_filename, kernel_cmdline, initrd_filename,
498 hwdefs[machine].machine_id);
501 /* SPARCstation 5 hardware initialisation */
502 static void ss5_init(int ram_size, int vga_ram_size, int boot_device,
503 DisplayState *ds, const char **fd_filename, int snapshot,
504 const char *kernel_filename, const char *kernel_cmdline,
505 const char *initrd_filename, const char *cpu_model)
507 if (cpu_model == NULL)
508 cpu_model = "Fujitsu MB86904";
509 sun4m_common_init(ram_size, boot_device, ds, kernel_filename,
510 kernel_cmdline, initrd_filename, cpu_model,
514 /* SPARCstation 10 hardware initialisation */
515 static void ss10_init(int ram_size, int vga_ram_size, int boot_device,
516 DisplayState *ds, const char **fd_filename, int snapshot,
517 const char *kernel_filename, const char *kernel_cmdline,
518 const char *initrd_filename, const char *cpu_model)
520 if (cpu_model == NULL)
521 cpu_model = "TI SuperSparc II";
522 sun4m_common_init(ram_size, boot_device, ds, kernel_filename,
523 kernel_cmdline, initrd_filename, cpu_model,
524 1, PROM_ADDR); // XXX prom overlap, actually first 4GB ok
527 QEMUMachine ss5_machine = {
529 "Sun4m platform, SPARCstation 5",
533 QEMUMachine ss10_machine = {
535 "Sun4m platform, SPARCstation 10",