2 * QEMU Sun4m System Emulator
4 * Copyright (c) 2003-2005 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
27 * Sun4m architecture was used in the following machines:
29 * SPARCserver 6xxMP/xx
30 * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15), SPARCclassic X (4/10)
31 * SPARCstation LX/ZX (4/30)
32 * SPARCstation Voyager
33 * SPARCstation 10/xx, SPARCserver 10/xx
34 * SPARCstation 5, SPARCserver 5
35 * SPARCstation 20/xx, SPARCserver 20
38 * See for example: http://www.sunhelp.org/faq/sunref1.html
41 #define KERNEL_LOAD_ADDR 0x00004000
42 #define CMDLINE_ADDR 0x007ff000
43 #define INITRD_LOAD_ADDR 0x00800000
44 #define PROM_SIZE_MAX (256 * 1024)
45 #define PROM_ADDR 0xffd00000
46 #define PROM_FILENAME "openbios-sparc32"
51 target_ulong iommu_base, slavio_base;
52 target_ulong intctl_base, counter_base, nvram_base, ms_kb_base, serial_base;
54 target_ulong dma_base, esp_base, le_base;
55 target_ulong tcx_base, cs_base;
56 long vram_size, nvram_size;
57 // IRQ numbers are not PIL ones, but master interrupt controller register
59 int intctl_g_intr, esp_irq, le_irq, cpu_irq, clock_irq, clock1_irq;
60 int ser_irq, ms_kb_irq, fd_irq, me_irq, cs_irq;
61 int machine_id; // For NVRAM
66 uint64_t cpu_get_tsc()
68 return qemu_get_clock(vm_clock);
71 int DMA_get_channel_mode (int nchan)
75 int DMA_read_memory (int nchan, void *buf, int pos, int size)
79 int DMA_write_memory (int nchan, void *buf, int pos, int size)
83 void DMA_hold_DREQ (int nchan) {}
84 void DMA_release_DREQ (int nchan) {}
85 void DMA_schedule(int nchan) {}
86 void DMA_run (void) {}
87 void DMA_init (int high_page_enable) {}
88 void DMA_register_channel (int nchan,
89 DMA_transfer_handler transfer_handler,
94 static void nvram_set_word (m48t59_t *nvram, uint32_t addr, uint16_t value)
96 m48t59_write(nvram, addr++, (value >> 8) & 0xff);
97 m48t59_write(nvram, addr++, value & 0xff);
100 static void nvram_set_lword (m48t59_t *nvram, uint32_t addr, uint32_t value)
102 m48t59_write(nvram, addr++, value >> 24);
103 m48t59_write(nvram, addr++, (value >> 16) & 0xff);
104 m48t59_write(nvram, addr++, (value >> 8) & 0xff);
105 m48t59_write(nvram, addr++, value & 0xff);
108 static void nvram_set_string (m48t59_t *nvram, uint32_t addr,
109 const unsigned char *str, uint32_t max)
113 for (i = 0; i < max && str[i] != '\0'; i++) {
114 m48t59_write(nvram, addr + i, str[i]);
116 m48t59_write(nvram, addr + max - 1, '\0');
119 static m48t59_t *nvram;
121 extern int nographic;
123 static void nvram_init(m48t59_t *nvram, uint8_t *macaddr, const char *cmdline,
124 int boot_device, uint32_t RAM_size,
125 uint32_t kernel_size,
126 int width, int height, int depth,
129 unsigned char tmp = 0;
132 // Try to match PPC NVRAM
133 nvram_set_string(nvram, 0x00, "QEMU_BIOS", 16);
134 nvram_set_lword(nvram, 0x10, 0x00000001); /* structure v1 */
135 // NVRAM_size, arch not applicable
136 m48t59_write(nvram, 0x2D, smp_cpus & 0xff);
137 m48t59_write(nvram, 0x2E, 0);
138 m48t59_write(nvram, 0x2F, nographic & 0xff);
139 nvram_set_lword(nvram, 0x30, RAM_size);
140 m48t59_write(nvram, 0x34, boot_device & 0xff);
141 nvram_set_lword(nvram, 0x38, KERNEL_LOAD_ADDR);
142 nvram_set_lword(nvram, 0x3C, kernel_size);
144 strcpy(phys_ram_base + CMDLINE_ADDR, cmdline);
145 nvram_set_lword(nvram, 0x40, CMDLINE_ADDR);
146 nvram_set_lword(nvram, 0x44, strlen(cmdline));
148 // initrd_image, initrd_size passed differently
149 nvram_set_word(nvram, 0x54, width);
150 nvram_set_word(nvram, 0x56, height);
151 nvram_set_word(nvram, 0x58, depth);
153 // Sun4m specific use
155 m48t59_write(nvram, i++, 0x01);
156 m48t59_write(nvram, i++, machine_id);
158 m48t59_write(nvram, i++, macaddr[j++]);
159 m48t59_write(nvram, i++, macaddr[j++]);
160 m48t59_write(nvram, i++, macaddr[j++]);
161 m48t59_write(nvram, i++, macaddr[j++]);
162 m48t59_write(nvram, i++, macaddr[j++]);
163 m48t59_write(nvram, i, macaddr[j]);
165 /* Calculate checksum */
166 for (i = 0x1fd8; i < 0x1fe7; i++) {
167 tmp ^= m48t59_read(nvram, i);
169 m48t59_write(nvram, 0x1fe7, tmp);
172 static void *slavio_intctl;
176 slavio_pic_info(slavio_intctl);
181 slavio_irq_info(slavio_intctl);
184 void pic_set_irq(int irq, int level)
186 slavio_pic_set_irq(slavio_intctl, irq, level);
189 void pic_set_irq_new(void *opaque, int irq, int level)
191 pic_set_irq(irq, level);
194 void pic_set_irq_cpu(int irq, int level, unsigned int cpu)
196 slavio_pic_set_irq_cpu(slavio_intctl, irq, level, cpu);
199 static void *slavio_misc;
201 void qemu_system_powerdown(void)
203 slavio_set_power_fail(slavio_misc, 1);
206 static void main_cpu_reset(void *opaque)
208 CPUState *env = opaque;
212 static void sun4m_hw_init(const struct hwdef *hwdef, int ram_size,
213 DisplayState *ds, const char *cpu_model)
216 CPUState *env, *envs[MAX_CPUS];
218 void *iommu, *dma, *main_esp, *main_lance = NULL;
219 const sparc_def_t *def;
222 sparc_find_by_name(cpu_model, &def);
224 fprintf(stderr, "Unable to find Sparc CPU definition\n");
227 for(i = 0; i < smp_cpus; i++) {
229 cpu_sparc_register(env, def);
233 register_savevm("cpu", i, 3, cpu_save, cpu_load, env);
234 qemu_register_reset(main_cpu_reset, env);
237 cpu_register_physical_memory(0, ram_size, 0);
239 iommu = iommu_init(hwdef->iommu_base);
240 slavio_intctl = slavio_intctl_init(hwdef->intctl_base,
241 hwdef->intctl_base + 0x10000);
242 for(i = 0; i < smp_cpus; i++) {
243 slavio_intctl_set_cpu(slavio_intctl, i, envs[i]);
245 dma = sparc32_dma_init(hwdef->dma_base, hwdef->esp_irq,
246 hwdef->le_irq, iommu, slavio_intctl);
248 tcx_init(ds, hwdef->tcx_base, phys_ram_base + ram_size, ram_size,
249 hwdef->vram_size, graphic_width, graphic_height);
250 if (nd_table[0].vlan) {
251 if (nd_table[0].model == NULL
252 || strcmp(nd_table[0].model, "lance") == 0) {
253 main_lance = lance_init(&nd_table[0], hwdef->le_base, dma);
255 fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model);
259 nvram = m48t59_init(0, hwdef->nvram_base, 0, hwdef->nvram_size, 8);
260 for (i = 0; i < MAX_CPUS; i++) {
261 slavio_timer_init(hwdef->counter_base + i * TARGET_PAGE_SIZE,
262 hwdef->clock_irq, 0, i);
264 slavio_timer_init(hwdef->counter_base + 0x10000, hwdef->clock1_irq, 2,
266 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, hwdef->ms_kb_irq);
267 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
268 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
269 slavio_serial_init(hwdef->serial_base, hwdef->ser_irq,
270 serial_hds[1], serial_hds[0]);
271 fdctrl_init(hwdef->fd_irq, 0, 1, hwdef->fd_base, fd_table);
272 main_esp = esp_init(bs_table, hwdef->esp_base, dma);
274 for (i = 0; i < MAX_DISKS; i++) {
276 esp_scsi_attach(main_esp, bs_table[i], i);
280 slavio_misc = slavio_misc_init(hwdef->slavio_base, hwdef->me_irq);
281 cs_init(hwdef->cs_base, hwdef->cs_irq, slavio_intctl);
282 sparc32_dma_set_reset_data(dma, main_esp, main_lance);
285 static void sun4m_load_kernel(long vram_size, int ram_size, int boot_device,
286 const char *kernel_filename,
287 const char *kernel_cmdline,
288 const char *initrd_filename,
294 long prom_offset, initrd_size, kernel_size;
296 linux_boot = (kernel_filename != NULL);
298 prom_offset = ram_size + vram_size;
299 cpu_register_physical_memory(PROM_ADDR,
300 (PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK,
301 prom_offset | IO_MEM_ROM);
303 snprintf(buf, sizeof(buf), "%s/%s", bios_dir, PROM_FILENAME);
304 ret = load_elf(buf, 0, NULL);
306 fprintf(stderr, "qemu: could not load prom '%s'\n",
313 kernel_size = load_elf(kernel_filename, -0xf0000000, NULL);
315 kernel_size = load_aout(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR);
317 kernel_size = load_image(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR);
318 if (kernel_size < 0) {
319 fprintf(stderr, "qemu: could not load kernel '%s'\n",
326 if (initrd_filename) {
327 initrd_size = load_image(initrd_filename, phys_ram_base + INITRD_LOAD_ADDR);
328 if (initrd_size < 0) {
329 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
334 if (initrd_size > 0) {
335 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
336 if (ldl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i)
337 == 0x48647253) { // HdrS
338 stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR);
339 stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 20, initrd_size);
345 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
346 boot_device, ram_size, kernel_size, graphic_width,
347 graphic_height, graphic_depth, machine_id);
350 static const struct hwdef hwdefs[] = {
353 .iommu_base = 0x10000000,
354 .tcx_base = 0x50000000,
355 .cs_base = 0x6c000000,
356 .slavio_base = 0x71000000,
357 .ms_kb_base = 0x71000000,
358 .serial_base = 0x71100000,
359 .nvram_base = 0x71200000,
360 .fd_base = 0x71400000,
361 .counter_base = 0x71d00000,
362 .intctl_base = 0x71e00000,
363 .dma_base = 0x78400000,
364 .esp_base = 0x78800000,
365 .le_base = 0x78c00000,
366 .vram_size = 0x00100000,
367 .nvram_size = 0x2000,
381 static void sun4m_common_init(int ram_size, int boot_device, DisplayState *ds,
382 const char *kernel_filename, const char *kernel_cmdline,
383 const char *initrd_filename, const char *cpu_model,
384 unsigned int machine)
386 sun4m_hw_init(&hwdefs[machine], ram_size, ds, cpu_model);
388 sun4m_load_kernel(hwdefs[machine].vram_size, ram_size, boot_device,
389 kernel_filename, kernel_cmdline, initrd_filename,
390 hwdefs[machine].machine_id);
393 /* SPARCstation 5 hardware initialisation */
394 static void ss5_init(int ram_size, int vga_ram_size, int boot_device,
395 DisplayState *ds, const char **fd_filename, int snapshot,
396 const char *kernel_filename, const char *kernel_cmdline,
397 const char *initrd_filename, const char *cpu_model)
399 if (cpu_model == NULL)
400 cpu_model = "Fujitsu MB86904";
401 sun4m_common_init(ram_size, boot_device, ds, kernel_filename,
402 kernel_cmdline, initrd_filename, cpu_model,
406 QEMUMachine ss5_machine = {
408 "Sun4m platform, SPARCstation 5",