2 * QEMU Sparc SLAVIO timer controller emulation
4 * Copyright (c) 2003-2005 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
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29 #define DPRINTF(fmt, args...) \
30 do { printf("TIMER: " fmt , ##args); } while (0)
32 #define DPRINTF(fmt, args...)
36 * Registers of hardware timer in sun4m.
38 * This is the timer/counter part of chip STP2001 (Slave I/O), also
39 * produced as NCR89C105. See
40 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
42 * The 31-bit counter is incremented every 500ns by bit 9. Bits 8..0
43 * are zero. Bit 31 is 1 when count has been reached.
45 * Per-CPU timers interrupt local CPU, system timer uses normal
50 typedef struct SLAVIO_TIMERState {
52 uint32_t count, counthigh, reached;
56 int mode; // 0 = processor, 1 = user, 2 = system
61 #define TIMER_MAXADDR 0x1f
63 // Update count, set irq, update expire_time
64 // Convert from ptimer countdown units
65 static void slavio_timer_get_out(SLAVIO_TIMERState *s)
69 count = s->limit - (ptimer_get_count(s->timer) << 9);
70 DPRINTF("get_out: limit %" PRIx64 " count %x%08x\n", s->limit, s->counthigh,
72 s->count = count & 0xfffffe00;
73 s->counthigh = count >> 32;
77 static void slavio_timer_irq(void *opaque)
79 SLAVIO_TIMERState *s = opaque;
81 slavio_timer_get_out(s);
82 DPRINTF("callback: count %x%08x\n", s->counthigh, s->count);
83 s->reached = 0x80000000;
85 pic_set_irq_cpu(s->intctl, s->irq, 1, s->cpu);
88 static uint32_t slavio_timer_mem_readl(void *opaque, target_phys_addr_t addr)
90 SLAVIO_TIMERState *s = opaque;
93 saddr = (addr & TIMER_MAXADDR) >> 2;
96 // read limit (system counter mode) or read most signifying
97 // part of counter (user mode)
100 pic_set_irq_cpu(s->intctl, s->irq, 0, s->cpu);
102 ret = s->limit & 0x7fffffff;
105 slavio_timer_get_out(s);
106 ret = s->counthigh & 0x7fffffff;
110 // read counter and reached bit (system mode) or read lsbits
111 // of counter (user mode)
112 slavio_timer_get_out(s);
114 ret = (s->count & 0x7fffffff) | s->reached;
119 // read start/stop status
123 // read user/system mode
130 DPRINTF("read " TARGET_FMT_plx " = %08x\n", addr, ret);
135 static void slavio_timer_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
137 SLAVIO_TIMERState *s = opaque;
141 DPRINTF("write " TARGET_FMT_plx " %08x\n", addr, val);
142 saddr = (addr & TIMER_MAXADDR) >> 2;
145 // set limit, reset counter
147 pic_set_irq_cpu(s->intctl, s->irq, 0, s->cpu);
150 // set limit without resetting counter
151 s->limit = val & 0x7ffffe00ULL;
153 s->limit = 0x7ffffe00ULL;
154 ptimer_set_limit(s->timer, s->limit >> 9, reload);
157 // start/stop user counter
160 ptimer_stop(s->timer);
164 ptimer_run(s->timer, 0);
170 // bit 0: user (1) or system (0) counter mode
171 if (s->mode == 0 || s->mode == 1)
174 pic_set_irq_cpu(s->intctl, s->irq, 0, s->cpu);
177 ptimer_set_limit(s->timer, s->limit >> 9, 1);
184 static CPUReadMemoryFunc *slavio_timer_mem_read[3] = {
185 slavio_timer_mem_readl,
186 slavio_timer_mem_readl,
187 slavio_timer_mem_readl,
190 static CPUWriteMemoryFunc *slavio_timer_mem_write[3] = {
191 slavio_timer_mem_writel,
192 slavio_timer_mem_writel,
193 slavio_timer_mem_writel,
196 static void slavio_timer_save(QEMUFile *f, void *opaque)
198 SLAVIO_TIMERState *s = opaque;
200 qemu_put_be64s(f, &s->limit);
201 qemu_put_be32s(f, &s->count);
202 qemu_put_be32s(f, &s->counthigh);
203 qemu_put_be32s(f, &s->irq);
204 qemu_put_be32s(f, &s->reached);
205 qemu_put_be32s(f, &s->stopped);
206 qemu_put_be32s(f, &s->mode);
207 qemu_put_ptimer(f, s->timer);
210 static int slavio_timer_load(QEMUFile *f, void *opaque, int version_id)
212 SLAVIO_TIMERState *s = opaque;
217 qemu_get_be64s(f, &s->limit);
218 qemu_get_be32s(f, &s->count);
219 qemu_get_be32s(f, &s->counthigh);
220 qemu_get_be32s(f, &s->irq);
221 qemu_get_be32s(f, &s->reached);
222 qemu_get_be32s(f, &s->stopped);
223 qemu_get_be32s(f, &s->mode);
224 qemu_get_ptimer(f, s->timer);
229 static void slavio_timer_reset(void *opaque)
231 SLAVIO_TIMERState *s = opaque;
233 s->limit = 0x7ffffe00ULL;
237 ptimer_set_limit(s->timer, s->limit >> 9, 1);
238 ptimer_run(s->timer, 0);
243 void slavio_timer_init(target_phys_addr_t addr, int irq, int mode,
244 unsigned int cpu, void *intctl)
246 int slavio_timer_io_memory;
247 SLAVIO_TIMERState *s;
250 s = qemu_mallocz(sizeof(SLAVIO_TIMERState));
256 bh = qemu_bh_new(slavio_timer_irq, s);
257 s->timer = ptimer_init(bh);
258 ptimer_set_period(s->timer, 500ULL);
261 slavio_timer_io_memory = cpu_register_io_memory(0, slavio_timer_mem_read,
262 slavio_timer_mem_write, s);
263 cpu_register_physical_memory(addr, TIMER_MAXADDR, slavio_timer_io_memory);
264 register_savevm("slavio_timer", addr, 2, slavio_timer_save, slavio_timer_load, s);
265 qemu_register_reset(slavio_timer_reset, s);
266 slavio_timer_reset(s);