2 * QEMU Sparc SLAVIO timer controller emulation
4 * Copyright (c) 2003-2005 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
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10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
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29 #define DPRINTF(fmt, args...) \
30 do { printf("TIMER: " fmt , ##args); } while (0)
31 #define pic_set_irq_new(intctl, irq, level) \
32 do { printf("TIMER: set_irq(%d): %d\n", (irq), (level)); \
33 pic_set_irq_new((intctl), (irq),(level));} while (0)
35 #define DPRINTF(fmt, args...)
39 * Registers of hardware timer in sun4m.
41 * This is the timer/counter part of chip STP2001 (Slave I/O), also
42 * produced as NCR89C105. See
43 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
45 * The 31-bit counter is incremented every 500ns by bit 9. Bits 8..0
46 * are zero. Bit 31 is 1 when count has been reached.
48 * Per-CPU timers interrupt local CPU, system timer uses normal
53 typedef struct SLAVIO_TIMERState {
54 uint32_t limit, count, counthigh;
55 int64_t count_load_time;
57 int64_t stop_time, tick_offset;
61 int mode; // 0 = processor, 1 = user, 2 = system
66 #define TIMER_MAXADDR 0x1f
67 #define CNT_FREQ 2000000
69 // Update count, set irq, update expire_time
70 static void slavio_timer_get_out(SLAVIO_TIMERState *s)
73 int64_t diff, ticks, count;
76 // There are three clock tick units: CPU ticks, register units
77 // (nanoseconds), and counter ticks (500 ns).
78 if (s->mode == 1 && s->stopped)
81 ticks = qemu_get_clock(vm_clock) - s->tick_offset;
83 out = (ticks > s->expire_time);
85 s->reached = 0x80000000;
91 // Convert register units to counter ticks
94 // Convert cpu ticks to counter ticks
95 diff = muldiv64(ticks - s->count_load_time, CNT_FREQ, ticks_per_sec);
97 // Calculate what the counter should be, convert to register
100 s->count = count << 9;
101 s->counthigh = count >> 22;
103 // Expire time: CPU ticks left to next interrupt
104 // Convert remaining counter ticks to CPU ticks
105 s->expire_time = ticks + muldiv64(limit - count, ticks_per_sec, CNT_FREQ);
107 DPRINTF("irq %d limit %d reached %d d %" PRId64 " count %d s->c %x diff %" PRId64 " stopped %d mode %d\n", s->irq, limit, s->reached?1:0, (ticks-s->count_load_time), count, s->count, s->expire_time - ticks, s->stopped, s->mode);
110 pic_set_irq_cpu(s->intctl, s->irq, out, s->cpu);
114 static void slavio_timer_irq(void *opaque)
116 SLAVIO_TIMERState *s = opaque;
120 slavio_timer_get_out(s);
122 qemu_mod_timer(s->irq_timer, s->expire_time);
125 static uint32_t slavio_timer_mem_readl(void *opaque, target_phys_addr_t addr)
127 SLAVIO_TIMERState *s = opaque;
130 saddr = (addr & TIMER_MAXADDR) >> 2;
133 // read limit (system counter mode) or read most signifying
134 // part of counter (user mode)
137 pic_set_irq_cpu(s->intctl, s->irq, 0, s->cpu);
142 slavio_timer_get_out(s);
143 return s->counthigh & 0x7fffffff;
146 // read counter and reached bit (system mode) or read lsbits
147 // of counter (user mode)
148 slavio_timer_get_out(s);
150 return (s->count & 0x7fffffff) | s->reached;
154 // read start/stop status
157 // read user/system mode
164 static void slavio_timer_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
166 SLAVIO_TIMERState *s = opaque;
169 saddr = (addr & TIMER_MAXADDR) >> 2;
172 // set limit, reset counter
173 s->count_load_time = qemu_get_clock(vm_clock);
176 // set limit without resetting counter
178 s->limit = 0x7fffffff;
180 s->limit = val & 0x7fffffff;
184 // start/stop user counter
187 s->stop_time = qemu_get_clock(vm_clock);
192 s->tick_offset += qemu_get_clock(vm_clock) - s->stop_time;
198 // bit 0: user (1) or system (0) counter mode
199 if (s->mode == 0 || s->mode == 1)
207 static CPUReadMemoryFunc *slavio_timer_mem_read[3] = {
208 slavio_timer_mem_readl,
209 slavio_timer_mem_readl,
210 slavio_timer_mem_readl,
213 static CPUWriteMemoryFunc *slavio_timer_mem_write[3] = {
214 slavio_timer_mem_writel,
215 slavio_timer_mem_writel,
216 slavio_timer_mem_writel,
219 static void slavio_timer_save(QEMUFile *f, void *opaque)
221 SLAVIO_TIMERState *s = opaque;
223 qemu_put_be32s(f, &s->limit);
224 qemu_put_be32s(f, &s->count);
225 qemu_put_be32s(f, &s->counthigh);
226 qemu_put_be64s(f, &s->count_load_time);
227 qemu_put_be64s(f, &s->expire_time);
228 qemu_put_be64s(f, &s->stop_time);
229 qemu_put_be64s(f, &s->tick_offset);
230 qemu_put_be32s(f, &s->irq);
231 qemu_put_be32s(f, &s->reached);
232 qemu_put_be32s(f, &s->stopped);
233 qemu_put_be32s(f, &s->mode);
236 static int slavio_timer_load(QEMUFile *f, void *opaque, int version_id)
238 SLAVIO_TIMERState *s = opaque;
243 qemu_get_be32s(f, &s->limit);
244 qemu_get_be32s(f, &s->count);
245 qemu_get_be32s(f, &s->counthigh);
246 qemu_get_be64s(f, &s->count_load_time);
247 qemu_get_be64s(f, &s->expire_time);
248 qemu_get_be64s(f, &s->stop_time);
249 qemu_get_be64s(f, &s->tick_offset);
250 qemu_get_be32s(f, &s->irq);
251 qemu_get_be32s(f, &s->reached);
252 qemu_get_be32s(f, &s->stopped);
253 qemu_get_be32s(f, &s->mode);
257 static void slavio_timer_reset(void *opaque)
259 SLAVIO_TIMERState *s = opaque;
263 s->count_load_time = qemu_get_clock(vm_clock);;
264 s->stop_time = s->count_load_time;
269 slavio_timer_get_out(s);
272 void slavio_timer_init(uint32_t addr, int irq, int mode, unsigned int cpu,
275 int slavio_timer_io_memory;
276 SLAVIO_TIMERState *s;
278 s = qemu_mallocz(sizeof(SLAVIO_TIMERState));
284 s->irq_timer = qemu_new_timer(vm_clock, slavio_timer_irq, s);
287 slavio_timer_io_memory = cpu_register_io_memory(0, slavio_timer_mem_read,
288 slavio_timer_mem_write, s);
289 cpu_register_physical_memory(addr, TIMER_MAXADDR, slavio_timer_io_memory);
290 register_savevm("slavio_timer", addr, 1, slavio_timer_save, slavio_timer_load, s);
291 qemu_register_reset(slavio_timer_reset, s);
292 slavio_timer_reset(s);