2 * QEMU Sparc SLAVIO aux io port emulation
4 * Copyright (c) 2005 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
32 * This is the auxio port, chip control and system control part of
33 * chip STP2001 (Slave I/O), also produced as NCR89C105. See
34 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
36 * This also includes the PMC CPU idle controller.
40 #define MISC_DPRINTF(fmt, args...) \
41 do { printf("MISC: " fmt , ##args); } while (0)
43 #define MISC_DPRINTF(fmt, args...)
46 typedef struct MiscState {
58 #define SYSCTRL_MAXADDR 3
59 #define SYSCTRL_SIZE (SYSCTRL_MAXADDR + 1)
61 #define LED_SIZE (LED_MAXADDR + 1)
63 #define MISC_MASK 0x0fff0000
64 #define MISC_LEDS 0x01600000
65 #define MISC_CFG 0x01800000
66 #define MISC_DIAG 0x01a00000
67 #define MISC_MDM 0x01b00000
68 #define MISC_SYS 0x01f00000
72 #define AUX2_PWROFF 0x01
73 #define AUX2_PWRINTCLR 0x02
74 #define AUX2_PWRFAIL 0x20
76 #define CFG_PWRINTEN 0x08
78 #define SYS_RESET 0x01
79 #define SYS_RESETSTAT 0x02
81 static void slavio_misc_update_irq(void *opaque)
83 MiscState *s = opaque;
85 if ((s->aux2 & AUX2_PWRFAIL) && (s->config & CFG_PWRINTEN)) {
86 MISC_DPRINTF("Raise IRQ\n");
87 qemu_irq_raise(s->irq);
89 MISC_DPRINTF("Lower IRQ\n");
90 qemu_irq_lower(s->irq);
94 static void slavio_misc_reset(void *opaque)
96 MiscState *s = opaque;
98 // Diagnostic and system control registers not cleared in reset
99 s->config = s->aux1 = s->aux2 = s->mctrl = 0;
102 void slavio_set_power_fail(void *opaque, int power_failing)
104 MiscState *s = opaque;
106 MISC_DPRINTF("Power fail: %d, config: %d\n", power_failing, s->config);
107 if (power_failing && (s->config & CFG_PWRINTEN)) {
108 s->aux2 |= AUX2_PWRFAIL;
110 s->aux2 &= ~AUX2_PWRFAIL;
112 slavio_misc_update_irq(s);
115 static void slavio_misc_mem_writeb(void *opaque, target_phys_addr_t addr,
118 MiscState *s = opaque;
120 switch (addr & MISC_MASK) {
122 MISC_DPRINTF("Write config %2.2x\n", val & 0xff);
123 s->config = val & 0xff;
124 slavio_misc_update_irq(s);
127 MISC_DPRINTF("Write diag %2.2x\n", val & 0xff);
128 s->diag = val & 0xff;
131 MISC_DPRINTF("Write modem control %2.2x\n", val & 0xff);
132 s->mctrl = val & 0xff;
139 static uint32_t slavio_misc_mem_readb(void *opaque, target_phys_addr_t addr)
141 MiscState *s = opaque;
144 switch (addr & MISC_MASK) {
147 MISC_DPRINTF("Read config %2.2x\n", ret);
151 MISC_DPRINTF("Read diag %2.2x\n", ret);
155 MISC_DPRINTF("Read modem control %2.2x\n", ret);
163 static CPUReadMemoryFunc *slavio_misc_mem_read[3] = {
164 slavio_misc_mem_readb,
169 static CPUWriteMemoryFunc *slavio_misc_mem_write[3] = {
170 slavio_misc_mem_writeb,
175 static void slavio_aux1_mem_writeb(void *opaque, target_phys_addr_t addr,
178 MiscState *s = opaque;
180 MISC_DPRINTF("Write aux1 %2.2x\n", val & 0xff);
182 // Send a pulse to floppy terminal count line
184 qemu_irq_raise(s->fdc_tc);
185 qemu_irq_lower(s->fdc_tc);
189 s->aux1 = val & 0xff;
192 static uint32_t slavio_aux1_mem_readb(void *opaque, target_phys_addr_t addr)
194 MiscState *s = opaque;
198 MISC_DPRINTF("Read aux1 %2.2x\n", ret);
203 static CPUReadMemoryFunc *slavio_aux1_mem_read[3] = {
204 slavio_aux1_mem_readb,
209 static CPUWriteMemoryFunc *slavio_aux1_mem_write[3] = {
210 slavio_aux1_mem_writeb,
215 static void slavio_aux2_mem_writeb(void *opaque, target_phys_addr_t addr,
218 MiscState *s = opaque;
220 val &= AUX2_PWRINTCLR | AUX2_PWROFF;
221 MISC_DPRINTF("Write aux2 %2.2x\n", val);
222 val |= s->aux2 & AUX2_PWRFAIL;
223 if (val & AUX2_PWRINTCLR) // Clear Power Fail int
226 if (val & AUX2_PWROFF)
227 qemu_system_shutdown_request();
228 slavio_misc_update_irq(s);
231 static uint32_t slavio_aux2_mem_readb(void *opaque, target_phys_addr_t addr)
233 MiscState *s = opaque;
237 MISC_DPRINTF("Read aux2 %2.2x\n", ret);
242 static CPUReadMemoryFunc *slavio_aux2_mem_read[3] = {
243 slavio_aux2_mem_readb,
248 static CPUWriteMemoryFunc *slavio_aux2_mem_write[3] = {
249 slavio_aux2_mem_writeb,
254 static void apc_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
256 MiscState *s = opaque;
258 MISC_DPRINTF("Write power management %2.2x\n", val & 0xff);
259 cpu_interrupt(s->env, CPU_INTERRUPT_HALT);
262 static uint32_t apc_mem_readb(void *opaque, target_phys_addr_t addr)
266 MISC_DPRINTF("Read power management %2.2x\n", ret);
270 static CPUReadMemoryFunc *apc_mem_read[3] = {
276 static CPUWriteMemoryFunc *apc_mem_write[3] = {
282 static uint32_t slavio_sysctrl_mem_readl(void *opaque, target_phys_addr_t addr)
284 MiscState *s = opaque;
285 uint32_t ret = 0, saddr;
287 saddr = addr & SYSCTRL_MAXADDR;
295 MISC_DPRINTF("Read system control reg 0x" TARGET_FMT_plx " = %x\n", addr,
300 static void slavio_sysctrl_mem_writel(void *opaque, target_phys_addr_t addr,
303 MiscState *s = opaque;
306 saddr = addr & SYSCTRL_MAXADDR;
307 MISC_DPRINTF("Write system control reg 0x" TARGET_FMT_plx " = %x\n", addr,
311 if (val & SYS_RESET) {
312 s->sysctrl = SYS_RESETSTAT;
313 qemu_system_reset_request();
321 static CPUReadMemoryFunc *slavio_sysctrl_mem_read[3] = {
324 slavio_sysctrl_mem_readl,
327 static CPUWriteMemoryFunc *slavio_sysctrl_mem_write[3] = {
330 slavio_sysctrl_mem_writel,
333 static uint32_t slavio_led_mem_readw(void *opaque, target_phys_addr_t addr)
335 MiscState *s = opaque;
336 uint32_t ret = 0, saddr;
338 saddr = addr & LED_MAXADDR;
346 MISC_DPRINTF("Read diagnostic LED reg 0x" TARGET_FMT_plx " = %x\n", addr,
351 static void slavio_led_mem_writew(void *opaque, target_phys_addr_t addr,
354 MiscState *s = opaque;
357 saddr = addr & LED_MAXADDR;
358 MISC_DPRINTF("Write diagnostic LED reg 0x" TARGET_FMT_plx " = %x\n", addr,
369 static CPUReadMemoryFunc *slavio_led_mem_read[3] = {
371 slavio_led_mem_readw,
375 static CPUWriteMemoryFunc *slavio_led_mem_write[3] = {
377 slavio_led_mem_writew,
381 static void slavio_misc_save(QEMUFile *f, void *opaque)
383 MiscState *s = opaque;
388 qemu_put_be32s(f, &tmp); /* ignored, was IRQ. */
389 qemu_put_8s(f, &s->config);
390 qemu_put_8s(f, &s->aux1);
391 qemu_put_8s(f, &s->aux2);
392 qemu_put_8s(f, &s->diag);
393 qemu_put_8s(f, &s->mctrl);
394 tmp8 = s->sysctrl & 0xff;
395 qemu_put_8s(f, &tmp8);
398 static int slavio_misc_load(QEMUFile *f, void *opaque, int version_id)
400 MiscState *s = opaque;
407 qemu_get_be32s(f, &tmp);
408 qemu_get_8s(f, &s->config);
409 qemu_get_8s(f, &s->aux1);
410 qemu_get_8s(f, &s->aux2);
411 qemu_get_8s(f, &s->diag);
412 qemu_get_8s(f, &s->mctrl);
413 qemu_get_8s(f, &tmp8);
414 s->sysctrl = (uint32_t)tmp8;
418 void *slavio_misc_init(target_phys_addr_t base, target_phys_addr_t power_base,
419 target_phys_addr_t aux1_base,
420 target_phys_addr_t aux2_base, qemu_irq irq,
421 CPUState *env, qemu_irq **fdc_tc)
426 s = qemu_mallocz(sizeof(MiscState));
431 /* 8 bit registers */
432 io = cpu_register_io_memory(0, slavio_misc_mem_read,
433 slavio_misc_mem_write, s);
435 cpu_register_physical_memory(base + MISC_CFG, MISC_SIZE, io);
437 cpu_register_physical_memory(base + MISC_DIAG, MISC_SIZE, io);
439 cpu_register_physical_memory(base + MISC_MDM, MISC_SIZE, io);
441 /* 16 bit registers */
442 io = cpu_register_io_memory(0, slavio_led_mem_read,
443 slavio_led_mem_write, s);
444 /* ss600mp diag LEDs */
445 cpu_register_physical_memory(base + MISC_LEDS, MISC_SIZE, io);
447 /* 32 bit registers */
448 io = cpu_register_io_memory(0, slavio_sysctrl_mem_read,
449 slavio_sysctrl_mem_write, s);
451 cpu_register_physical_memory(base + MISC_SYS, SYSCTRL_SIZE, io);
454 // AUX 1 (Misc System Functions)
456 io = cpu_register_io_memory(0, slavio_aux1_mem_read,
457 slavio_aux1_mem_write, s);
458 cpu_register_physical_memory(aux1_base, MISC_SIZE, io);
461 // AUX 2 (Software Powerdown Control)
463 io = cpu_register_io_memory(0, slavio_aux2_mem_read,
464 slavio_aux2_mem_write, s);
465 cpu_register_physical_memory(aux2_base, MISC_SIZE, io);
468 // Power management (APC) XXX: not a Slavio device
470 io = cpu_register_io_memory(0, apc_mem_read, apc_mem_write, s);
471 cpu_register_physical_memory(power_base, MISC_SIZE, io);
476 *fdc_tc = &s->fdc_tc;
478 register_savevm("slavio_misc", base, 1, slavio_misc_save, slavio_misc_load,
480 qemu_register_reset(slavio_misc_reset, s);
481 slavio_misc_reset(s);