2 * QEMU Sparc SLAVIO interrupt controller emulation
4 * Copyright (c) 2003-2005 Fabrice Bellard
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25 //#define DEBUG_IRQ_COUNT
29 #define DPRINTF(fmt, args...) \
30 do { printf("IRQ: " fmt , ##args); } while (0)
32 #define DPRINTF(fmt, args...)
36 * Registers of interrupt controller in sun4m.
38 * This is the interrupt controller part of chip STP2001 (Slave I/O), also
39 * produced as NCR89C105. See
40 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
42 * There is a system master controller and one for each cpu.
48 typedef struct SLAVIO_INTCTLState {
49 uint32_t intreg_pending[MAX_CPUS];
50 uint32_t intregm_pending;
51 uint32_t intregm_disabled;
53 #ifdef DEBUG_IRQ_COUNT
54 uint64_t irq_count[32];
58 #define INTCTL_MAXADDR 0xf
59 #define INTCTLM_MAXADDR 0xf
60 static void slavio_check_interrupts(void *opaque);
62 // per-cpu interrupt controller
63 static uint32_t slavio_intctl_mem_readl(void *opaque, target_phys_addr_t addr)
65 SLAVIO_INTCTLState *s = opaque;
69 cpu = (addr & (MAX_CPUS - 1) * TARGET_PAGE_SIZE) >> 12;
70 saddr = (addr & INTCTL_MAXADDR) >> 2;
73 return s->intreg_pending[cpu];
80 static void slavio_intctl_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
82 SLAVIO_INTCTLState *s = opaque;
86 cpu = (addr & (MAX_CPUS - 1) * TARGET_PAGE_SIZE) >> 12;
87 saddr = (addr & INTCTL_MAXADDR) >> 2;
89 case 1: // clear pending softints
93 s->intreg_pending[cpu] &= ~val;
94 DPRINTF("Cleared cpu %d irq mask %x, curmask %x\n", cpu, val, s->intreg_pending[cpu]);
96 case 2: // set softint
98 s->intreg_pending[cpu] |= val;
99 DPRINTF("Set cpu %d irq mask %x, curmask %x\n", cpu, val, s->intreg_pending[cpu]);
106 static CPUReadMemoryFunc *slavio_intctl_mem_read[3] = {
107 slavio_intctl_mem_readl,
108 slavio_intctl_mem_readl,
109 slavio_intctl_mem_readl,
112 static CPUWriteMemoryFunc *slavio_intctl_mem_write[3] = {
113 slavio_intctl_mem_writel,
114 slavio_intctl_mem_writel,
115 slavio_intctl_mem_writel,
118 // master system interrupt controller
119 static uint32_t slavio_intctlm_mem_readl(void *opaque, target_phys_addr_t addr)
121 SLAVIO_INTCTLState *s = opaque;
124 saddr = (addr & INTCTLM_MAXADDR) >> 2;
127 return s->intregm_pending & 0x7fffffff;
129 return s->intregm_disabled;
131 return s->target_cpu;
138 static void slavio_intctlm_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
140 SLAVIO_INTCTLState *s = opaque;
143 saddr = (addr & INTCTLM_MAXADDR) >> 2;
145 case 2: // clear (enable)
146 // Force clear unused bits
148 s->intregm_disabled &= ~val;
149 DPRINTF("Enabled master irq mask %x, curmask %x\n", val, s->intregm_disabled);
150 slavio_check_interrupts(s);
152 case 3: // set (disable, clear pending)
153 // Force clear unused bits
155 s->intregm_disabled |= val;
156 s->intregm_pending &= ~val;
157 DPRINTF("Disabled master irq mask %x, curmask %x\n", val, s->intregm_disabled);
160 s->target_cpu = val & (MAX_CPUS - 1);
161 DPRINTF("Set master irq cpu %d\n", s->target_cpu);
168 static CPUReadMemoryFunc *slavio_intctlm_mem_read[3] = {
169 slavio_intctlm_mem_readl,
170 slavio_intctlm_mem_readl,
171 slavio_intctlm_mem_readl,
174 static CPUWriteMemoryFunc *slavio_intctlm_mem_write[3] = {
175 slavio_intctlm_mem_writel,
176 slavio_intctlm_mem_writel,
177 slavio_intctlm_mem_writel,
180 void slavio_pic_info(void *opaque)
182 SLAVIO_INTCTLState *s = opaque;
185 for (i = 0; i < MAX_CPUS; i++) {
186 term_printf("per-cpu %d: pending 0x%08x\n", i, s->intreg_pending[i]);
188 term_printf("master: pending 0x%08x, disabled 0x%08x\n", s->intregm_pending, s->intregm_disabled);
191 void slavio_irq_info(void *opaque)
193 #ifndef DEBUG_IRQ_COUNT
194 term_printf("irq statistic code not compiled.\n");
196 SLAVIO_INTCTLState *s = opaque;
200 term_printf("IRQ statistics:\n");
201 for (i = 0; i < 32; i++) {
202 count = s->irq_count[i];
204 term_printf("%2d: %lld\n", i, count);
209 static const uint32_t intbit_to_level[32] = {
210 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
211 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
214 static void slavio_check_interrupts(void *opaque)
217 SLAVIO_INTCTLState *s = opaque;
218 uint32_t pending = s->intregm_pending;
219 unsigned int i, max = 0;
221 pending &= ~s->intregm_disabled;
223 if (pending && !(s->intregm_disabled & 0x80000000)) {
224 for (i = 0; i < 32; i++) {
225 if (pending & (1 << i)) {
226 if (max < intbit_to_level[i])
227 max = intbit_to_level[i];
231 if (env->interrupt_index == 0) {
232 DPRINTF("Triggered pil %d\n", max);
233 #ifdef DEBUG_IRQ_COUNT
236 env->interrupt_index = TT_EXTINT | max;
237 cpu_interrupt(env, CPU_INTERRUPT_HARD);
240 DPRINTF("Not triggered (pending %x), pending exception %x\n", pending, env->interrupt_index);
243 DPRINTF("Not triggered (pending %x), disabled %x\n", pending, s->intregm_disabled);
247 * "irq" here is the bit number in the system interrupt register to
248 * separate serial and keyboard interrupts sharing a level.
250 void slavio_pic_set_irq(void *opaque, int irq, int level)
252 SLAVIO_INTCTLState *s = opaque;
254 DPRINTF("Set irq %d level %d\n", irq, level);
256 uint32_t mask = 1 << irq;
257 uint32_t pil = intbit_to_level[irq];
260 s->intregm_pending |= mask;
261 s->intreg_pending[s->target_cpu] |= 1 << pil;
264 s->intregm_pending &= ~mask;
265 s->intreg_pending[s->target_cpu] &= ~(1 << pil);
269 slavio_check_interrupts(s);
272 static void slavio_intctl_save(QEMUFile *f, void *opaque)
274 SLAVIO_INTCTLState *s = opaque;
277 for (i = 0; i < MAX_CPUS; i++) {
278 qemu_put_be32s(f, &s->intreg_pending[i]);
280 qemu_put_be32s(f, &s->intregm_pending);
281 qemu_put_be32s(f, &s->intregm_disabled);
282 qemu_put_be32s(f, &s->target_cpu);
285 static int slavio_intctl_load(QEMUFile *f, void *opaque, int version_id)
287 SLAVIO_INTCTLState *s = opaque;
293 for (i = 0; i < MAX_CPUS; i++) {
294 qemu_get_be32s(f, &s->intreg_pending[i]);
296 qemu_get_be32s(f, &s->intregm_pending);
297 qemu_get_be32s(f, &s->intregm_disabled);
298 qemu_get_be32s(f, &s->target_cpu);
302 static void slavio_intctl_reset(void *opaque)
304 SLAVIO_INTCTLState *s = opaque;
307 for (i = 0; i < MAX_CPUS; i++) {
308 s->intreg_pending[i] = 0;
310 s->intregm_disabled = ~0xffb2007f;
311 s->intregm_pending = 0;
315 void *slavio_intctl_init(uint32_t addr, uint32_t addrg)
317 int slavio_intctl_io_memory, slavio_intctlm_io_memory, i;
318 SLAVIO_INTCTLState *s;
320 s = qemu_mallocz(sizeof(SLAVIO_INTCTLState));
324 for (i = 0; i < MAX_CPUS; i++) {
325 slavio_intctl_io_memory = cpu_register_io_memory(0, slavio_intctl_mem_read, slavio_intctl_mem_write, s);
326 cpu_register_physical_memory(addr + i * TARGET_PAGE_SIZE, INTCTL_MAXADDR, slavio_intctl_io_memory);
329 slavio_intctlm_io_memory = cpu_register_io_memory(0, slavio_intctlm_mem_read, slavio_intctlm_mem_write, s);
330 cpu_register_physical_memory(addrg, INTCTLM_MAXADDR, slavio_intctlm_io_memory);
332 register_savevm("slavio_intctl", addr, 1, slavio_intctl_save, slavio_intctl_load, s);
333 qemu_register_reset(slavio_intctl_reset, s);
334 slavio_intctl_reset(s);