2 * QEMU Sparc SLAVIO interrupt controller emulation
4 * Copyright (c) 2003-2005 Fabrice Bellard
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7 * of this software and associated documentation files (the "Software"), to deal
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25 //#define DEBUG_IRQ_COUNT
29 #define DPRINTF(fmt, args...) \
30 do { printf("IRQ: " fmt , ##args); } while (0)
32 #define DPRINTF(fmt, args...)
36 * Registers of interrupt controller in sun4m.
38 * This is the interrupt controller part of chip STP2001 (Slave I/O), also
39 * produced as NCR89C105. See
40 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
42 * There is a system master controller and one for each cpu.
48 typedef struct SLAVIO_INTCTLState {
49 uint32_t intreg_pending[MAX_CPUS];
50 uint32_t intregm_pending;
51 uint32_t intregm_disabled;
53 #ifdef DEBUG_IRQ_COUNT
54 uint64_t irq_count[32];
56 CPUState *cpu_envs[MAX_CPUS];
57 const uint32_t *intbit_to_level;
60 #define INTCTL_MAXADDR 0xf
61 #define INTCTLM_MAXADDR 0x13
62 #define INTCTLM_MASK 0x1f
63 static void slavio_check_interrupts(void *opaque);
65 // per-cpu interrupt controller
66 static uint32_t slavio_intctl_mem_readl(void *opaque, target_phys_addr_t addr)
68 SLAVIO_INTCTLState *s = opaque;
72 cpu = (addr & (MAX_CPUS - 1) * TARGET_PAGE_SIZE) >> 12;
73 saddr = (addr & INTCTL_MAXADDR) >> 2;
76 return s->intreg_pending[cpu];
83 static void slavio_intctl_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
85 SLAVIO_INTCTLState *s = opaque;
89 cpu = (addr & (MAX_CPUS - 1) * TARGET_PAGE_SIZE) >> 12;
90 saddr = (addr & INTCTL_MAXADDR) >> 2;
92 case 1: // clear pending softints
96 s->intreg_pending[cpu] &= ~val;
97 DPRINTF("Cleared cpu %d irq mask %x, curmask %x\n", cpu, val, s->intreg_pending[cpu]);
99 case 2: // set softint
101 s->intreg_pending[cpu] |= val;
102 slavio_check_interrupts(s);
103 DPRINTF("Set cpu %d irq mask %x, curmask %x\n", cpu, val, s->intreg_pending[cpu]);
110 static CPUReadMemoryFunc *slavio_intctl_mem_read[3] = {
111 slavio_intctl_mem_readl,
112 slavio_intctl_mem_readl,
113 slavio_intctl_mem_readl,
116 static CPUWriteMemoryFunc *slavio_intctl_mem_write[3] = {
117 slavio_intctl_mem_writel,
118 slavio_intctl_mem_writel,
119 slavio_intctl_mem_writel,
122 // master system interrupt controller
123 static uint32_t slavio_intctlm_mem_readl(void *opaque, target_phys_addr_t addr)
125 SLAVIO_INTCTLState *s = opaque;
128 saddr = (addr & INTCTLM_MAXADDR) >> 2;
131 return s->intregm_pending & 0x7fffffff;
133 return s->intregm_disabled;
135 return s->target_cpu;
142 static void slavio_intctlm_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
144 SLAVIO_INTCTLState *s = opaque;
147 saddr = (addr & INTCTLM_MASK) >> 2;
149 case 2: // clear (enable)
150 // Force clear unused bits
152 s->intregm_disabled &= ~val;
153 DPRINTF("Enabled master irq mask %x, curmask %x\n", val, s->intregm_disabled);
154 slavio_check_interrupts(s);
156 case 3: // set (disable, clear pending)
157 // Force clear unused bits
159 s->intregm_disabled |= val;
160 s->intregm_pending &= ~val;
161 DPRINTF("Disabled master irq mask %x, curmask %x\n", val, s->intregm_disabled);
164 s->target_cpu = val & (MAX_CPUS - 1);
165 DPRINTF("Set master irq cpu %d\n", s->target_cpu);
172 static CPUReadMemoryFunc *slavio_intctlm_mem_read[3] = {
173 slavio_intctlm_mem_readl,
174 slavio_intctlm_mem_readl,
175 slavio_intctlm_mem_readl,
178 static CPUWriteMemoryFunc *slavio_intctlm_mem_write[3] = {
179 slavio_intctlm_mem_writel,
180 slavio_intctlm_mem_writel,
181 slavio_intctlm_mem_writel,
184 void slavio_pic_info(void *opaque)
186 SLAVIO_INTCTLState *s = opaque;
189 for (i = 0; i < MAX_CPUS; i++) {
190 term_printf("per-cpu %d: pending 0x%08x\n", i, s->intreg_pending[i]);
192 term_printf("master: pending 0x%08x, disabled 0x%08x\n", s->intregm_pending, s->intregm_disabled);
195 void slavio_irq_info(void *opaque)
197 #ifndef DEBUG_IRQ_COUNT
198 term_printf("irq statistic code not compiled.\n");
200 SLAVIO_INTCTLState *s = opaque;
204 term_printf("IRQ statistics:\n");
205 for (i = 0; i < 32; i++) {
206 count = s->irq_count[i];
208 term_printf("%2d: %" PRId64 "\n", i, count);
213 static void slavio_check_interrupts(void *opaque)
216 SLAVIO_INTCTLState *s = opaque;
217 uint32_t pending = s->intregm_pending;
218 unsigned int i, j, max = 0;
220 pending &= ~s->intregm_disabled;
222 if (pending && !(s->intregm_disabled & 0x80000000)) {
223 for (i = 0; i < 32; i++) {
224 if (pending & (1 << i)) {
225 if (max < s->intbit_to_level[i])
226 max = s->intbit_to_level[i];
229 env = s->cpu_envs[s->target_cpu];
231 DPRINTF("No CPU %d, not triggered (pending %x)\n", s->target_cpu, pending);
236 if (env->interrupt_index == 0) {
237 DPRINTF("Triggered CPU %d pil %d\n", s->target_cpu, max);
238 #ifdef DEBUG_IRQ_COUNT
241 env->interrupt_index = TT_EXTINT | max;
242 cpu_interrupt(env, CPU_INTERRUPT_HARD);
245 DPRINTF("Not triggered (pending %x), pending exception %x\n", pending, env->interrupt_index);
249 DPRINTF("Not triggered (pending %x), disabled %x\n", pending, s->intregm_disabled);
251 for (i = 0; i < MAX_CPUS; i++) {
253 env = s->cpu_envs[i];
256 for (j = 17; j < 32; j++) {
257 if (s->intreg_pending[i] & (1 << j)) {
265 if (env->interrupt_index == 0) {
266 DPRINTF("Triggered softint %d for cpu %d (pending %x)\n", max, i, pending);
267 #ifdef DEBUG_IRQ_COUNT
270 env->interrupt_index = TT_EXTINT | max;
271 cpu_interrupt(env, CPU_INTERRUPT_HARD);
278 * "irq" here is the bit number in the system interrupt register to
279 * separate serial and keyboard interrupts sharing a level.
281 void slavio_set_irq(void *opaque, int irq, int level)
283 SLAVIO_INTCTLState *s = opaque;
285 DPRINTF("Set cpu %d irq %d level %d\n", s->target_cpu, irq, level);
287 uint32_t mask = 1 << irq;
288 uint32_t pil = s->intbit_to_level[irq];
291 s->intregm_pending |= mask;
292 s->intreg_pending[s->target_cpu] |= 1 << pil;
293 slavio_check_interrupts(s);
296 s->intregm_pending &= ~mask;
297 s->intreg_pending[s->target_cpu] &= ~(1 << pil);
303 void pic_set_irq_cpu(void *opaque, int irq, int level, unsigned int cpu)
305 SLAVIO_INTCTLState *s = opaque;
307 DPRINTF("Set cpu %d local irq %d level %d\n", cpu, irq, level);
308 if (cpu == (unsigned int)-1) {
309 slavio_set_irq(opaque, irq, level);
313 uint32_t pil = s->intbit_to_level[irq];
316 s->intreg_pending[cpu] |= 1 << pil;
319 s->intreg_pending[cpu] &= ~(1 << pil);
323 slavio_check_interrupts(s);
326 static void slavio_intctl_save(QEMUFile *f, void *opaque)
328 SLAVIO_INTCTLState *s = opaque;
331 for (i = 0; i < MAX_CPUS; i++) {
332 qemu_put_be32s(f, &s->intreg_pending[i]);
334 qemu_put_be32s(f, &s->intregm_pending);
335 qemu_put_be32s(f, &s->intregm_disabled);
336 qemu_put_be32s(f, &s->target_cpu);
339 static int slavio_intctl_load(QEMUFile *f, void *opaque, int version_id)
341 SLAVIO_INTCTLState *s = opaque;
347 for (i = 0; i < MAX_CPUS; i++) {
348 qemu_get_be32s(f, &s->intreg_pending[i]);
350 qemu_get_be32s(f, &s->intregm_pending);
351 qemu_get_be32s(f, &s->intregm_disabled);
352 qemu_get_be32s(f, &s->target_cpu);
356 static void slavio_intctl_reset(void *opaque)
358 SLAVIO_INTCTLState *s = opaque;
361 for (i = 0; i < MAX_CPUS; i++) {
362 s->intreg_pending[i] = 0;
364 s->intregm_disabled = ~0xffb2007f;
365 s->intregm_pending = 0;
369 void slavio_intctl_set_cpu(void *opaque, unsigned int cpu, CPUState *env)
371 SLAVIO_INTCTLState *s = opaque;
372 s->cpu_envs[cpu] = env;
375 void *slavio_intctl_init(target_phys_addr_t addr, target_phys_addr_t addrg,
376 const uint32_t *intbit_to_level,
379 int slavio_intctl_io_memory, slavio_intctlm_io_memory, i;
380 SLAVIO_INTCTLState *s;
382 s = qemu_mallocz(sizeof(SLAVIO_INTCTLState));
386 s->intbit_to_level = intbit_to_level;
387 for (i = 0; i < MAX_CPUS; i++) {
388 slavio_intctl_io_memory = cpu_register_io_memory(0, slavio_intctl_mem_read, slavio_intctl_mem_write, s);
389 cpu_register_physical_memory(addr + i * TARGET_PAGE_SIZE, INTCTL_MAXADDR, slavio_intctl_io_memory);
392 slavio_intctlm_io_memory = cpu_register_io_memory(0, slavio_intctlm_mem_read, slavio_intctlm_mem_write, s);
393 cpu_register_physical_memory(addrg, INTCTLM_MAXADDR, slavio_intctlm_io_memory);
395 register_savevm("slavio_intctl", addr, 1, slavio_intctl_save, slavio_intctl_load, s);
396 qemu_register_reset(slavio_intctl_reset, s);
397 *irq = qemu_allocate_irqs(slavio_set_irq, s, 32);
398 slavio_intctl_reset(s);