2 * QEMU 16450 UART emulation
4 * Copyright (c) 2003-2004 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 //#define DEBUG_SERIAL
28 #define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
30 #define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
31 #define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
32 #define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
33 #define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
35 #define UART_IIR_NO_INT 0x01 /* No interrupts pending */
36 #define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
38 #define UART_IIR_MSI 0x00 /* Modem status interrupt */
39 #define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
40 #define UART_IIR_RDI 0x04 /* Receiver data interrupt */
41 #define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
44 * These are the definitions for the Modem Control Register
46 #define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
47 #define UART_MCR_OUT2 0x08 /* Out2 complement */
48 #define UART_MCR_OUT1 0x04 /* Out1 complement */
49 #define UART_MCR_RTS 0x02 /* RTS complement */
50 #define UART_MCR_DTR 0x01 /* DTR complement */
53 * These are the definitions for the Modem Status Register
55 #define UART_MSR_DCD 0x80 /* Data Carrier Detect */
56 #define UART_MSR_RI 0x40 /* Ring Indicator */
57 #define UART_MSR_DSR 0x20 /* Data Set Ready */
58 #define UART_MSR_CTS 0x10 /* Clear to Send */
59 #define UART_MSR_DDCD 0x08 /* Delta DCD */
60 #define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */
61 #define UART_MSR_DDSR 0x02 /* Delta DSR */
62 #define UART_MSR_DCTS 0x01 /* Delta CTS */
63 #define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */
65 #define UART_LSR_TEMT 0x40 /* Transmitter empty */
66 #define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
67 #define UART_LSR_BI 0x10 /* Break interrupt indicator */
68 #define UART_LSR_FE 0x08 /* Frame error indicator */
69 #define UART_LSR_PE 0x04 /* Parity error indicator */
70 #define UART_LSR_OE 0x02 /* Overrun error indicator */
71 #define UART_LSR_DR 0x01 /* Receiver data ready */
75 uint8_t rbr; /* receive register */
77 uint8_t iir; /* read only */
80 uint8_t lsr; /* read only */
83 /* NOTE: this hidden state is necessary for tx irq generation as
84 it can be reset while reading iir */
90 static void serial_update_irq(SerialState *s)
92 if ((s->lsr & UART_LSR_DR) && (s->ier & UART_IER_RDI)) {
93 s->iir = UART_IIR_RDI;
94 } else if (s->thr_ipending && (s->ier & UART_IER_THRI)) {
95 s->iir = UART_IIR_THRI;
97 s->iir = UART_IIR_NO_INT;
99 if (s->iir != UART_IIR_NO_INT) {
100 pic_set_irq(s->irq, 1);
102 pic_set_irq(s->irq, 0);
106 static void serial_ioport_write(void *opaque, uint32_t addr, uint32_t val)
108 SerialState *s = opaque;
114 printf("serial: write addr=0x%02x val=0x%02x\n", addr, val);
119 if (s->lcr & UART_LCR_DLAB) {
120 s->divider = (s->divider & 0xff00) | val;
123 s->lsr &= ~UART_LSR_THRE;
124 serial_update_irq(s);
126 if (s->out_fd >= 0) {
129 ret = write(s->out_fd, &ch, 1);
133 s->lsr |= UART_LSR_THRE;
134 s->lsr |= UART_LSR_TEMT;
135 serial_update_irq(s);
139 if (s->lcr & UART_LCR_DLAB) {
140 s->divider = (s->divider & 0x00ff) | (val << 8);
143 serial_update_irq(s);
165 static uint32_t serial_ioport_read(void *opaque, uint32_t addr)
167 SerialState *s = opaque;
174 if (s->lcr & UART_LCR_DLAB) {
175 ret = s->divider & 0xff;
178 s->lsr &= ~(UART_LSR_DR | UART_LSR_BI);
179 serial_update_irq(s);
183 if (s->lcr & UART_LCR_DLAB) {
184 ret = (s->divider >> 8) & 0xff;
191 /* reset THR pending bit */
192 if ((ret & 0x7) == UART_IIR_THRI)
194 serial_update_irq(s);
206 if (s->mcr & UART_MCR_LOOP) {
207 /* in loopback, the modem output pins are connected to the
209 ret = (s->mcr & 0x0c) << 4;
210 ret |= (s->mcr & 0x02) << 3;
211 ret |= (s->mcr & 0x01) << 5;
221 printf("serial: read addr=0x%02x val=0x%02x\n", addr, ret);
226 int serial_can_receive(SerialState *s)
228 return !(s->lsr & UART_LSR_DR);
231 void serial_receive_byte(SerialState *s, int ch)
234 s->lsr |= UART_LSR_DR;
235 serial_update_irq(s);
238 void serial_receive_break(SerialState *s)
241 s->lsr |= UART_LSR_BI | UART_LSR_DR;
242 serial_update_irq(s);
245 static int serial_can_receive1(void *opaque)
247 SerialState *s = opaque;
248 return serial_can_receive(s);
251 static void serial_receive1(void *opaque, const uint8_t *buf, int size)
253 SerialState *s = opaque;
254 serial_receive_byte(s, buf[0]);
257 /* If fd is zero, it means that the serial device uses the console */
258 SerialState *serial_init(int base, int irq, int fd)
262 s = qemu_mallocz(sizeof(SerialState));
266 s->lsr = UART_LSR_TEMT | UART_LSR_THRE;
267 s->iir = UART_IIR_NO_INT;
269 register_ioport_write(base, 8, 1, serial_ioport_write, s);
270 register_ioport_read(base, 8, 1, serial_ioport_read, s);
273 /* no associated device */
275 } else if (fd != 0) {
276 qemu_add_fd_read_handler(fd, serial_can_receive1, serial_receive1, s);