2 * Intel XScale PXA255/270 OS Timers.
4 * Copyright (c) 2006 Openedhand Ltd.
5 * Copyright (c) 2006 Thorsten Zitterell
7 * This code is licenced under the GPL.
24 #define OSCR 0x10 /* OS Timer Count */
33 #define OSSR 0x14 /* Timer status register */
35 #define OIER 0x1c /* Interrupt enable register 3-0 to E3-E0 */
36 #define OMCR4 0xc0 /* OS Match Control registers */
46 #define PXA25X_FREQ 3686400 /* 3.6864 MHz */
47 #define PXA27X_FREQ 3250000 /* 3.25 MHz */
49 static int pxa2xx_timer4_freq[8] = {
55 /* [5] is the "Externally supplied clock". Assign if necessary. */
59 struct pxa2xx_timer0_s {
68 struct pxa2xx_timer4_s {
69 struct pxa2xx_timer0_s tm;
83 struct pxa2xx_timer0_s timer[4];
84 struct pxa2xx_timer4_s *tm4;
93 static void pxa2xx_timer_update(void *opaque, uint64_t now_qemu)
95 pxa2xx_timer_info *s = (pxa2xx_timer_info *) opaque;
101 muldiv64(now_qemu - s->lastload, s->freq, ticks_per_sec);
103 for (i = 0; i < 4; i ++) {
104 new_qemu = now_qemu + muldiv64((uint32_t) (s->timer[i].value - now_vm),
105 ticks_per_sec, s->freq);
106 qemu_mod_timer(s->timer[i].qtimer, new_qemu);
110 static void pxa2xx_timer_update4(void *opaque, uint64_t now_qemu, int n)
112 pxa2xx_timer_info *s = (pxa2xx_timer_info *) opaque;
115 static const int counters[8] = { 0, 0, 0, 0, 4, 4, 6, 6 };
118 if (s->tm4[n].control & (1 << 7))
121 counter = counters[n];
123 if (!s->tm4[counter].freq) {
124 qemu_del_timer(s->timer[n].qtimer);
128 now_vm = s->tm4[counter].clock + muldiv64(now_qemu -
129 s->tm4[counter].lastload,
130 s->tm4[counter].freq, ticks_per_sec);
132 new_qemu = now_qemu + muldiv64((uint32_t) (s->tm4[n].tm.value - now_vm),
133 ticks_per_sec, s->tm4[counter].freq);
134 qemu_mod_timer(s->timer[n].qtimer, new_qemu);
137 static uint32_t pxa2xx_timer_read(void *opaque, target_phys_addr_t offset)
139 pxa2xx_timer_info *s = (pxa2xx_timer_info *) opaque;
149 return s->timer[tm].value;
160 return s->tm4[tm].tm.value;
162 return s->clock + muldiv64(qemu_get_clock(vm_clock) -
163 s->lastload, s->freq, ticks_per_sec);
175 if ((tm == 9 - 4 || tm == 11 - 4) && (s->tm4[tm].control & (1 << 9))) {
176 if (s->tm4[tm - 1].freq)
177 s->snapshot = s->tm4[tm - 1].clock + muldiv64(
178 qemu_get_clock(vm_clock) -
179 s->tm4[tm - 1].lastload,
180 s->tm4[tm - 1].freq, ticks_per_sec);
182 s->snapshot = s->tm4[tm - 1].clock;
185 if (!s->tm4[tm].freq)
186 return s->tm4[tm].clock;
187 return s->tm4[tm].clock + muldiv64(qemu_get_clock(vm_clock) -
188 s->tm4[tm].lastload, s->tm4[tm].freq, ticks_per_sec);
190 return s->irq_enabled;
191 case OSSR: /* Status register */
205 return s->tm4[tm].control;
210 cpu_abort(cpu_single_env, "pxa2xx_timer_read: Bad offset "
211 REG_FMT "\n", offset);
217 static void pxa2xx_timer_write(void *opaque, target_phys_addr_t offset,
221 pxa2xx_timer_info *s = (pxa2xx_timer_info *) opaque;
230 s->timer[tm].value = value;
231 pxa2xx_timer_update(s, qemu_get_clock(vm_clock));
243 s->tm4[tm].tm.value = value;
244 pxa2xx_timer_update4(s, qemu_get_clock(vm_clock), tm);
247 s->oldclock = s->clock;
248 s->lastload = qemu_get_clock(vm_clock);
250 pxa2xx_timer_update(s, s->lastload);
262 s->tm4[tm].oldclock = s->tm4[tm].clock;
263 s->tm4[tm].lastload = qemu_get_clock(vm_clock);
264 s->tm4[tm].clock = value;
265 pxa2xx_timer_update4(s, s->tm4[tm].lastload, tm);
268 s->irq_enabled = value & 0xfff;
270 case OSSR: /* Status register */
272 for (i = 0; i < 4; i ++, value >>= 1) {
273 if (s->timer[i].level && (value & 1)) {
274 s->timer[i].level = 0;
275 qemu_irq_lower(s->timer[i].irq);
279 for (i = 0; i < 8; i ++, value >>= 1)
280 if (s->tm4[i].tm.level && (value & 1))
281 s->tm4[i].tm.level = 0;
282 if (!(s->events & 0xff0))
283 qemu_irq_lower(s->tm4->tm.irq);
286 case OWER: /* XXX: Reset on OSMR3 match? */
295 s->tm4[tm].control = value & 0x0ff;
296 /* XXX Stop if running (shouldn't happen) */
297 if ((value & (1 << 7)) || tm == 0)
298 s->tm4[tm].freq = pxa2xx_timer4_freq[value & 7];
301 pxa2xx_timer_update4(s, qemu_get_clock(vm_clock), tm);
310 s->tm4[tm].control = value & 0x3ff;
311 /* XXX Stop if running (shouldn't happen) */
312 if ((value & (1 << 7)) || !(tm & 1))
314 pxa2xx_timer4_freq[(value & (1 << 8)) ? 0 : (value & 7)];
317 pxa2xx_timer_update4(s, qemu_get_clock(vm_clock), tm);
322 cpu_abort(cpu_single_env, "pxa2xx_timer_write: Bad offset "
323 REG_FMT "\n", offset);
327 static CPUReadMemoryFunc *pxa2xx_timer_readfn[] = {
333 static CPUWriteMemoryFunc *pxa2xx_timer_writefn[] = {
339 static void pxa2xx_timer_tick(void *opaque)
341 struct pxa2xx_timer0_s *t = (struct pxa2xx_timer0_s *) opaque;
342 pxa2xx_timer_info *i = (pxa2xx_timer_info *) t->info;
344 if (i->irq_enabled & (1 << t->num)) {
346 i->events |= 1 << t->num;
347 qemu_irq_raise(t->irq);
353 cpu_reset(i->cpustate);
357 static void pxa2xx_timer_tick4(void *opaque)
359 struct pxa2xx_timer4_s *t = (struct pxa2xx_timer4_s *) opaque;
360 pxa2xx_timer_info *i = (pxa2xx_timer_info *) t->tm.info;
362 pxa2xx_timer_tick(&t->tm);
363 if (t->control & (1 << 3))
365 if (t->control & (1 << 6))
366 pxa2xx_timer_update4(i, qemu_get_clock(vm_clock), t->tm.num - 4);
369 static pxa2xx_timer_info *pxa2xx_timer_init(target_phys_addr_t base,
370 qemu_irq *irqs, CPUState *cpustate)
374 pxa2xx_timer_info *s;
376 s = (pxa2xx_timer_info *) qemu_mallocz(sizeof(pxa2xx_timer_info));
381 s->lastload = qemu_get_clock(vm_clock);
383 s->cpustate = cpustate;
385 for (i = 0; i < 4; i ++) {
386 s->timer[i].value = 0;
387 s->timer[i].irq = irqs[i];
388 s->timer[i].info = s;
390 s->timer[i].level = 0;
391 s->timer[i].qtimer = qemu_new_timer(vm_clock,
392 pxa2xx_timer_tick, &s->timer[i]);
395 iomemtype = cpu_register_io_memory(0, pxa2xx_timer_readfn,
396 pxa2xx_timer_writefn, s);
397 cpu_register_physical_memory(base, 0x00000fff, iomemtype);
401 void pxa25x_timer_init(target_phys_addr_t base,
402 qemu_irq *irqs, CPUState *cpustate)
404 pxa2xx_timer_info *s = pxa2xx_timer_init(base, irqs, cpustate);
405 s->freq = PXA25X_FREQ;
409 void pxa27x_timer_init(target_phys_addr_t base,
410 qemu_irq *irqs, qemu_irq irq4, CPUState *cpustate)
412 pxa2xx_timer_info *s = pxa2xx_timer_init(base, irqs, cpustate);
414 s->freq = PXA27X_FREQ;
415 s->tm4 = (struct pxa2xx_timer4_s *) qemu_mallocz(8 *
416 sizeof(struct pxa2xx_timer4_s));
417 for (i = 0; i < 8; i ++) {
418 s->tm4[i].tm.value = 0;
419 s->tm4[i].tm.irq = irq4;
420 s->tm4[i].tm.info = s;
421 s->tm4[i].tm.num = i + 4;
422 s->tm4[i].tm.level = 0;
424 s->tm4[i].control = 0x0;
425 s->tm4[i].tm.qtimer = qemu_new_timer(vm_clock,
426 pxa2xx_timer_tick4, &s->tm4[i]);