2 * Intel XScale PXA255/270 OS Timers.
4 * Copyright (c) 2006 Openedhand Ltd.
5 * Copyright (c) 2006 Thorsten Zitterell
7 * This code is licenced under the GPL.
24 #define OSCR 0x10 /* OS Timer Count */
33 #define OSSR 0x14 /* Timer status register */
35 #define OIER 0x1c /* Interrupt enable register 3-0 to E3-E0 */
36 #define OMCR4 0xc0 /* OS Match Control registers */
46 #define PXA25X_FREQ 3686400 /* 3.6864 MHz */
47 #define PXA27X_FREQ 3250000 /* 3.25 MHz */
49 static int pxa2xx_timer4_freq[8] = {
55 /* [5] is the "Externally supplied clock". Assign if necessary. */
59 struct pxa2xx_timer0_s {
68 struct pxa2xx_timer4_s {
88 struct pxa2xx_timer0_s timer[4];
89 struct pxa2xx_timer4_s *tm4;
98 static void pxa2xx_timer_update(void *opaque, uint64_t now_qemu)
100 pxa2xx_timer_info *s = (pxa2xx_timer_info *) opaque;
106 muldiv64(now_qemu - s->lastload, s->freq, ticks_per_sec);
108 for (i = 0; i < 4; i ++) {
109 new_qemu = now_qemu + muldiv64((uint32_t) (s->timer[i].value - now_vm),
110 ticks_per_sec, s->freq);
111 qemu_mod_timer(s->timer[i].qtimer, new_qemu);
115 static void pxa2xx_timer_update4(void *opaque, uint64_t now_qemu, int n)
117 pxa2xx_timer_info *s = (pxa2xx_timer_info *) opaque;
120 static const int counters[8] = { 0, 0, 0, 0, 4, 4, 6, 6 };
123 if (s->tm4[n].control & (1 << 7))
126 counter = counters[n];
128 if (!s->tm4[counter].freq) {
129 qemu_del_timer(s->timer[n].qtimer);
133 now_vm = s->tm4[counter].clock + muldiv64(now_qemu -
134 s->tm4[counter].lastload,
135 s->tm4[counter].freq, ticks_per_sec);
137 new_qemu = now_qemu + muldiv64((uint32_t) (s->tm4[n].value - now_vm),
138 ticks_per_sec, s->tm4[counter].freq);
139 qemu_mod_timer(s->timer[n].qtimer, new_qemu);
142 static uint32_t pxa2xx_timer_read(void *opaque, target_phys_addr_t offset)
144 pxa2xx_timer_info *s = (pxa2xx_timer_info *) opaque;
154 return s->timer[tm].value;
165 return s->tm4[tm].value;
167 return s->clock + muldiv64(qemu_get_clock(vm_clock) -
168 s->lastload, s->freq, ticks_per_sec);
180 if ((tm == 9 - 4 || tm == 11 - 4) && (s->tm4[tm].control & (1 << 9))) {
181 if (s->tm4[tm - 1].freq)
182 s->snapshot = s->tm4[tm - 1].clock + muldiv64(
183 qemu_get_clock(vm_clock) -
184 s->tm4[tm - 1].lastload,
185 s->tm4[tm - 1].freq, ticks_per_sec);
187 s->snapshot = s->tm4[tm - 1].clock;
190 if (!s->tm4[tm].freq)
191 return s->tm4[tm].clock;
192 return s->tm4[tm].clock + muldiv64(qemu_get_clock(vm_clock) -
193 s->tm4[tm].lastload, s->tm4[tm].freq, ticks_per_sec);
195 return s->irq_enabled;
196 case OSSR: /* Status register */
210 return s->tm4[tm].control;
215 cpu_abort(cpu_single_env, "pxa2xx_timer_read: Bad offset "
216 REG_FMT "\n", offset);
222 static void pxa2xx_timer_write(void *opaque, target_phys_addr_t offset,
226 pxa2xx_timer_info *s = (pxa2xx_timer_info *) opaque;
235 s->timer[tm].value = value;
236 pxa2xx_timer_update(s, qemu_get_clock(vm_clock));
248 s->tm4[tm].value = value;
249 pxa2xx_timer_update4(s, qemu_get_clock(vm_clock), tm);
252 s->oldclock = s->clock;
253 s->lastload = qemu_get_clock(vm_clock);
255 pxa2xx_timer_update(s, s->lastload);
267 s->tm4[tm].oldclock = s->tm4[tm].clock;
268 s->tm4[tm].lastload = qemu_get_clock(vm_clock);
269 s->tm4[tm].clock = value;
270 pxa2xx_timer_update4(s, s->tm4[tm].lastload, tm);
273 s->irq_enabled = value & 0xfff;
275 case OSSR: /* Status register */
277 for (i = 0; i < 4; i ++, value >>= 1) {
278 if (s->timer[i].level && (value & 1)) {
279 s->timer[i].level = 0;
280 qemu_irq_lower(s->timer[i].irq);
284 for (i = 0; i < 8; i ++, value >>= 1)
285 if (s->tm4[i].level && (value & 1))
287 if (!(s->events & 0xff0))
288 qemu_irq_lower(s->tm4->irq);
291 case OWER: /* XXX: Reset on OSMR3 match? */
300 s->tm4[tm].control = value & 0x0ff;
301 /* XXX Stop if running (shouldn't happen) */
302 if ((value & (1 << 7)) || tm == 0)
303 s->tm4[tm].freq = pxa2xx_timer4_freq[value & 7];
306 pxa2xx_timer_update4(s, qemu_get_clock(vm_clock), tm);
315 s->tm4[tm].control = value & 0x3ff;
316 /* XXX Stop if running (shouldn't happen) */
317 if ((value & (1 << 7)) || !(tm & 1))
319 pxa2xx_timer4_freq[(value & (1 << 8)) ? 0 : (value & 7)];
322 pxa2xx_timer_update4(s, qemu_get_clock(vm_clock), tm);
327 cpu_abort(cpu_single_env, "pxa2xx_timer_write: Bad offset "
328 REG_FMT "\n", offset);
332 static CPUReadMemoryFunc *pxa2xx_timer_readfn[] = {
338 static CPUWriteMemoryFunc *pxa2xx_timer_writefn[] = {
344 static void pxa2xx_timer_tick(void *opaque)
346 struct pxa2xx_timer0_s *t = (struct pxa2xx_timer0_s *) opaque;
347 pxa2xx_timer_info *i = (pxa2xx_timer_info *) t->info;
349 if (i->irq_enabled & (1 << t->num)) {
351 i->events |= 1 << t->num;
352 qemu_irq_raise(t->irq);
358 cpu_reset(i->cpustate);
362 static void pxa2xx_timer_tick4(void *opaque)
364 struct pxa2xx_timer4_s *t = (struct pxa2xx_timer4_s *) opaque;
365 pxa2xx_timer_info *i = (pxa2xx_timer_info *) t->info;
367 pxa2xx_timer_tick4(opaque);
368 if (t->control & (1 << 3))
370 if (t->control & (1 << 6))
371 pxa2xx_timer_update4(i, qemu_get_clock(vm_clock), t->num - 4);
374 static pxa2xx_timer_info *pxa2xx_timer_init(target_phys_addr_t base,
375 qemu_irq *irqs, CPUState *cpustate)
379 pxa2xx_timer_info *s;
381 s = (pxa2xx_timer_info *) qemu_mallocz(sizeof(pxa2xx_timer_info));
386 s->lastload = qemu_get_clock(vm_clock);
388 s->cpustate = cpustate;
390 for (i = 0; i < 4; i ++) {
391 s->timer[i].value = 0;
392 s->timer[i].irq = irqs[i];
393 s->timer[i].info = s;
395 s->timer[i].level = 0;
396 s->timer[i].qtimer = qemu_new_timer(vm_clock,
397 pxa2xx_timer_tick, &s->timer[i]);
400 iomemtype = cpu_register_io_memory(0, pxa2xx_timer_readfn,
401 pxa2xx_timer_writefn, s);
402 cpu_register_physical_memory(base, 0x00000fff, iomemtype);
406 void pxa25x_timer_init(target_phys_addr_t base,
407 qemu_irq *irqs, CPUState *cpustate)
409 pxa2xx_timer_info *s = pxa2xx_timer_init(base, irqs, cpustate);
410 s->freq = PXA25X_FREQ;
414 void pxa27x_timer_init(target_phys_addr_t base,
415 qemu_irq *irqs, qemu_irq irq4, CPUState *cpustate)
417 pxa2xx_timer_info *s = pxa2xx_timer_init(base, irqs, cpustate);
419 s->freq = PXA27X_FREQ;
420 s->tm4 = (struct pxa2xx_timer4_s *) qemu_mallocz(8 *
421 sizeof(struct pxa2xx_timer4_s));
422 for (i = 0; i < 8; i ++) {
424 s->tm4[i].irq = irq4;
426 s->tm4[i].num = i + 4;
429 s->tm4[i].control = 0x0;
430 s->tm4[i].qtimer = qemu_new_timer(vm_clock,
431 pxa2xx_timer_tick4, &s->tm4[i]);