2 * Intel XScale PXA255/270 MultiMediaCard/SD/SDIO Controller emulation.
4 * Copyright (c) 2006 Openedhand Ltd.
5 * Written by Andrzej Zaborowski <balrog@zabor.org>
7 * This code is licensed under the GPLv2.
13 struct pxa2xx_mmci_s {
14 target_phys_addr_t base;
41 uint16_t resp_fifo[9];
48 #define MMC_STRPCL 0x00 /* MMC Clock Start/Stop register */
49 #define MMC_STAT 0x04 /* MMC Status register */
50 #define MMC_CLKRT 0x08 /* MMC Clock Rate register */
51 #define MMC_SPI 0x0c /* MMC SPI Mode register */
52 #define MMC_CMDAT 0x10 /* MMC Command/Data register */
53 #define MMC_RESTO 0x14 /* MMC Response Time-Out register */
54 #define MMC_RDTO 0x18 /* MMC Read Time-Out register */
55 #define MMC_BLKLEN 0x1c /* MMC Block Length register */
56 #define MMC_NUMBLK 0x20 /* MMC Number of Blocks register */
57 #define MMC_PRTBUF 0x24 /* MMC Buffer Partly Full register */
58 #define MMC_I_MASK 0x28 /* MMC Interrupt Mask register */
59 #define MMC_I_REG 0x2c /* MMC Interrupt Request register */
60 #define MMC_CMD 0x30 /* MMC Command register */
61 #define MMC_ARGH 0x34 /* MMC Argument High register */
62 #define MMC_ARGL 0x38 /* MMC Argument Low register */
63 #define MMC_RES 0x3c /* MMC Response FIFO */
64 #define MMC_RXFIFO 0x40 /* MMC Receive FIFO */
65 #define MMC_TXFIFO 0x44 /* MMC Transmit FIFO */
66 #define MMC_RDWAIT 0x48 /* MMC RD_WAIT register */
67 #define MMC_BLKS_REM 0x4c /* MMC Blocks Remaining register */
70 #define STRPCL_STOP_CLK (1 << 0)
71 #define STRPCL_STRT_CLK (1 << 1)
72 #define STAT_TOUT_RES (1 << 1)
73 #define STAT_CLK_EN (1 << 8)
74 #define STAT_DATA_DONE (1 << 11)
75 #define STAT_PRG_DONE (1 << 12)
76 #define STAT_END_CMDRES (1 << 13)
77 #define SPI_SPI_MODE (1 << 0)
78 #define CMDAT_RES_TYPE (3 << 0)
79 #define CMDAT_DATA_EN (1 << 2)
80 #define CMDAT_WR_RD (1 << 3)
81 #define CMDAT_DMA_EN (1 << 7)
82 #define CMDAT_STOP_TRAN (1 << 10)
83 #define INT_DATA_DONE (1 << 0)
84 #define INT_PRG_DONE (1 << 1)
85 #define INT_END_CMD (1 << 2)
86 #define INT_STOP_CMD (1 << 3)
87 #define INT_CLK_OFF (1 << 4)
88 #define INT_RXFIFO_REQ (1 << 5)
89 #define INT_TXFIFO_REQ (1 << 6)
90 #define INT_TINT (1 << 7)
91 #define INT_DAT_ERR (1 << 8)
92 #define INT_RES_ERR (1 << 9)
93 #define INT_RD_STALLED (1 << 10)
94 #define INT_SDIO_INT (1 << 11)
95 #define INT_SDIO_SACK (1 << 12)
96 #define PRTBUF_PRT_BUF (1 << 0)
98 /* Route internal interrupt lines to the global IC and DMA */
99 static void pxa2xx_mmci_int_update(struct pxa2xx_mmci_s *s)
101 uint32_t mask = s->intmask;
102 if (s->cmdat & CMDAT_DMA_EN) {
103 mask |= INT_RXFIFO_REQ | INT_TXFIFO_REQ;
105 pxa2xx_dma_request((struct pxa2xx_dma_state_s *) s->dma,
106 PXA2XX_RX_RQ_MMCI, !!(s->intreq & INT_RXFIFO_REQ));
107 pxa2xx_dma_request((struct pxa2xx_dma_state_s *) s->dma,
108 PXA2XX_TX_RQ_MMCI, !!(s->intreq & INT_TXFIFO_REQ));
111 qemu_set_irq(s->irq, !!(s->intreq & ~mask));
114 static void pxa2xx_mmci_fifo_update(struct pxa2xx_mmci_s *s)
119 if (s->cmdat & CMDAT_WR_RD) {
120 while (s->bytesleft && s->tx_len) {
121 sd_write_data(s->card, s->tx_fifo[s->tx_start ++]);
127 s->intreq |= INT_TXFIFO_REQ;
129 while (s->bytesleft && s->rx_len < 32) {
130 s->rx_fifo[(s->rx_start + (s->rx_len ++)) & 0x1f] =
131 sd_read_data(s->card);
133 s->intreq |= INT_RXFIFO_REQ;
138 s->intreq |= INT_DATA_DONE;
139 s->status |= STAT_DATA_DONE;
141 if (s->cmdat & CMDAT_WR_RD) {
142 s->intreq |= INT_PRG_DONE;
143 s->status |= STAT_PRG_DONE;
147 pxa2xx_mmci_int_update(s);
150 static void pxa2xx_mmci_wakequeues(struct pxa2xx_mmci_s *s)
153 struct sd_request_s request;
154 uint8_t response[16];
161 request.cmd = s->cmd;
162 request.arg = s->arg;
163 request.crc = 0; /* FIXME */
165 rsplen = sd_do_command(s->card, &request, response);
166 s->intreq |= INT_END_CMD;
168 memset(s->resp_fifo, 0, sizeof(s->resp_fifo));
169 switch (s->cmdat & CMDAT_RES_TYPE) {
170 #define PXAMMCI_RESP(wd, value0, value1) \
171 s->resp_fifo[(wd) + 0] |= (value0); \
172 s->resp_fifo[(wd) + 1] |= (value1) << 8;
173 case 0: /* No response */
176 case 1: /* R1, R4, R5 or R6 */
192 for (i = 0; rsplen > 0; i ++, rsplen -= 2) {
193 PXAMMCI_RESP(i, response[i * 2], response[i * 2 + 1]);
195 s->status |= STAT_END_CMDRES;
197 if (!(s->cmdat & CMDAT_DATA_EN))
200 s->bytesleft = s->numblk * s->blklen;
207 s->status |= STAT_TOUT_RES;
211 pxa2xx_mmci_fifo_update(s);
214 static uint32_t pxa2xx_mmci_read(void *opaque, target_phys_addr_t offset)
216 struct pxa2xx_mmci_s *s = (struct pxa2xx_mmci_s *) opaque;
246 return s->cmd | 0x40;
250 return s->arg & 0xffff;
253 return s->resp_fifo[s->resp_len ++];
257 while (s->ac_width -- && s->rx_len) {
258 ret |= s->rx_fifo[s->rx_start ++] << (s->ac_width << 3);
262 s->intreq &= ~INT_RXFIFO_REQ;
263 pxa2xx_mmci_fifo_update(s);
270 cpu_abort(cpu_single_env, "%s: Bad offset " REG_FMT "\n",
271 __FUNCTION__, offset);
277 static void pxa2xx_mmci_write(void *opaque,
278 target_phys_addr_t offset, uint32_t value)
280 struct pxa2xx_mmci_s *s = (struct pxa2xx_mmci_s *) opaque;
285 if (value & STRPCL_STRT_CLK) {
286 s->status |= STAT_CLK_EN;
287 s->intreq &= ~INT_CLK_OFF;
289 if (s->cmdreq && !(s->cmdat & CMDAT_STOP_TRAN)) {
290 s->status &= STAT_CLK_EN;
291 pxa2xx_mmci_wakequeues(s);
295 if (value & STRPCL_STOP_CLK) {
296 s->status &= ~STAT_CLK_EN;
297 s->intreq |= INT_CLK_OFF;
301 pxa2xx_mmci_int_update(s);
305 s->clkrt = value & 7;
309 s->spi = value & 0xf;
310 if (value & SPI_SPI_MODE)
311 printf("%s: attempted to use card in SPI mode\n", __FUNCTION__);
315 s->cmdat = value & 0x3dff;
318 if (!(value & CMDAT_STOP_TRAN)) {
319 s->status &= STAT_CLK_EN;
321 if (s->status & STAT_CLK_EN)
322 pxa2xx_mmci_wakequeues(s);
325 pxa2xx_mmci_int_update(s);
329 s->resp_tout = value & 0x7f;
333 s->read_tout = value & 0xffff;
337 s->blklen = value & 0xfff;
341 s->numblk = value & 0xffff;
345 if (value & PRTBUF_PRT_BUF) {
349 pxa2xx_mmci_fifo_update(s);
353 s->intmask = value & 0x1fff;
354 pxa2xx_mmci_int_update(s);
358 s->cmd = value & 0x3f;
362 s->arg &= 0x0000ffff;
363 s->arg |= value << 16;
367 s->arg &= 0xffff0000;
368 s->arg |= value & 0x0000ffff;
372 while (s->ac_width -- && s->tx_len < 0x20)
373 s->tx_fifo[(s->tx_start + (s->tx_len ++)) & 0x1f] =
374 (value >> (s->ac_width << 3)) & 0xff;
375 s->intreq &= ~INT_TXFIFO_REQ;
376 pxa2xx_mmci_fifo_update(s);
384 cpu_abort(cpu_single_env, "%s: Bad offset " REG_FMT "\n",
385 __FUNCTION__, offset);
389 static uint32_t pxa2xx_mmci_readb(void *opaque, target_phys_addr_t offset)
391 struct pxa2xx_mmci_s *s = (struct pxa2xx_mmci_s *) opaque;
393 return pxa2xx_mmci_read(opaque, offset);
396 static uint32_t pxa2xx_mmci_readh(void *opaque, target_phys_addr_t offset)
398 struct pxa2xx_mmci_s *s = (struct pxa2xx_mmci_s *) opaque;
400 return pxa2xx_mmci_read(opaque, offset);
403 static uint32_t pxa2xx_mmci_readw(void *opaque, target_phys_addr_t offset)
405 struct pxa2xx_mmci_s *s = (struct pxa2xx_mmci_s *) opaque;
407 return pxa2xx_mmci_read(opaque, offset);
410 static CPUReadMemoryFunc *pxa2xx_mmci_readfn[] = {
416 static void pxa2xx_mmci_writeb(void *opaque,
417 target_phys_addr_t offset, uint32_t value)
419 struct pxa2xx_mmci_s *s = (struct pxa2xx_mmci_s *) opaque;
421 pxa2xx_mmci_write(opaque, offset, value);
424 static void pxa2xx_mmci_writeh(void *opaque,
425 target_phys_addr_t offset, uint32_t value)
427 struct pxa2xx_mmci_s *s = (struct pxa2xx_mmci_s *) opaque;
429 pxa2xx_mmci_write(opaque, offset, value);
432 static void pxa2xx_mmci_writew(void *opaque,
433 target_phys_addr_t offset, uint32_t value)
435 struct pxa2xx_mmci_s *s = (struct pxa2xx_mmci_s *) opaque;
437 pxa2xx_mmci_write(opaque, offset, value);
440 static CPUWriteMemoryFunc *pxa2xx_mmci_writefn[] = {
446 struct pxa2xx_mmci_s *pxa2xx_mmci_init(target_phys_addr_t base,
447 qemu_irq irq, void *dma)
450 struct pxa2xx_mmci_s *s;
452 s = (struct pxa2xx_mmci_s *) qemu_mallocz(sizeof(struct pxa2xx_mmci_s));
457 iomemtype = cpu_register_io_memory(0, pxa2xx_mmci_readfn,
458 pxa2xx_mmci_writefn, s);
459 cpu_register_physical_memory(base, 0x000fffff, iomemtype);
461 /* Instantiate the actual storage */
462 s->card = sd_init(sd_bdrv);
467 void pxa2xx_mmci_handlers(struct pxa2xx_mmci_s *s, void *opaque,
468 void (*readonly_cb)(void *, int),
469 void (*coverswitch_cb)(void *, int))
471 sd_set_cb(s->card, opaque, readonly_cb, coverswitch_cb);