2 * Intel XScale PXA255/270 LCDC emulation.
4 * Copyright (c) 2006 Openedhand Ltd.
5 * Written by Andrzej Zaborowski <balrog@zabor.org>
7 * This code is licensed under the GPLv2.
11 #include "pixel_ops.h"
13 typedef void (*drawfn)(uint32_t *, uint8_t *, const uint8_t *, int, int);
15 struct pxa2xx_lcdc_s {
16 target_phys_addr_t base;
52 target_phys_addr_t branch;
54 uint8_t palette[1024];
55 uint8_t pbuffer[1024];
56 void (*redraw)(struct pxa2xx_lcdc_s *s, uint8_t *fb,
57 int *miny, int *maxy);
59 target_phys_addr_t descriptor;
60 target_phys_addr_t source;
65 void (*vsync_cb)(void *opaque);
70 struct __attribute__ ((__packed__)) pxa_frame_descriptor_s {
77 #define LCCR0 0x000 /* LCD Controller Control register 0 */
78 #define LCCR1 0x004 /* LCD Controller Control register 1 */
79 #define LCCR2 0x008 /* LCD Controller Control register 2 */
80 #define LCCR3 0x00c /* LCD Controller Control register 3 */
81 #define LCCR4 0x010 /* LCD Controller Control register 4 */
82 #define LCCR5 0x014 /* LCD Controller Control register 5 */
84 #define FBR0 0x020 /* DMA Channel 0 Frame Branch register */
85 #define FBR1 0x024 /* DMA Channel 1 Frame Branch register */
86 #define FBR2 0x028 /* DMA Channel 2 Frame Branch register */
87 #define FBR3 0x02c /* DMA Channel 3 Frame Branch register */
88 #define FBR4 0x030 /* DMA Channel 4 Frame Branch register */
89 #define FBR5 0x110 /* DMA Channel 5 Frame Branch register */
90 #define FBR6 0x114 /* DMA Channel 6 Frame Branch register */
92 #define LCSR1 0x034 /* LCD Controller Status register 1 */
93 #define LCSR0 0x038 /* LCD Controller Status register 0 */
94 #define LIIDR 0x03c /* LCD Controller Interrupt ID register */
96 #define TRGBR 0x040 /* TMED RGB Seed register */
97 #define TCR 0x044 /* TMED Control register */
99 #define OVL1C1 0x050 /* Overlay 1 Control register 1 */
100 #define OVL1C2 0x060 /* Overlay 1 Control register 2 */
101 #define OVL2C1 0x070 /* Overlay 2 Control register 1 */
102 #define OVL2C2 0x080 /* Overlay 2 Control register 2 */
103 #define CCR 0x090 /* Cursor Control register */
105 #define CMDCR 0x100 /* Command Control register */
106 #define PRSR 0x104 /* Panel Read Status register */
108 #define PXA_LCDDMA_CHANS 7
109 #define DMA_FDADR 0x00 /* Frame Descriptor Address register */
110 #define DMA_FSADR 0x04 /* Frame Source Address register */
111 #define DMA_FIDR 0x08 /* Frame ID register */
112 #define DMA_LDCMD 0x0c /* Command register */
114 /* LCD Buffer Strength Control register */
115 #define BSCNTR 0x04000054
118 #define LCCR0_ENB (1 << 0)
119 #define LCCR0_CMS (1 << 1)
120 #define LCCR0_SDS (1 << 2)
121 #define LCCR0_LDM (1 << 3)
122 #define LCCR0_SOFM0 (1 << 4)
123 #define LCCR0_IUM (1 << 5)
124 #define LCCR0_EOFM0 (1 << 6)
125 #define LCCR0_PAS (1 << 7)
126 #define LCCR0_DPD (1 << 9)
127 #define LCCR0_DIS (1 << 10)
128 #define LCCR0_QDM (1 << 11)
129 #define LCCR0_PDD (0xff << 12)
130 #define LCCR0_BSM0 (1 << 20)
131 #define LCCR0_OUM (1 << 21)
132 #define LCCR0_LCDT (1 << 22)
133 #define LCCR0_RDSTM (1 << 23)
134 #define LCCR0_CMDIM (1 << 24)
135 #define LCCR0_OUC (1 << 25)
136 #define LCCR0_LDDALT (1 << 26)
137 #define LCCR1_PPL(x) ((x) & 0x3ff)
138 #define LCCR2_LPP(x) ((x) & 0x3ff)
139 #define LCCR3_API (15 << 16)
140 #define LCCR3_BPP(x) ((((x) >> 24) & 7) | (((x) >> 26) & 8))
141 #define LCCR3_PDFOR(x) (((x) >> 30) & 3)
142 #define LCCR4_K1(x) (((x) >> 0) & 7)
143 #define LCCR4_K2(x) (((x) >> 3) & 7)
144 #define LCCR4_K3(x) (((x) >> 6) & 7)
145 #define LCCR4_PALFOR(x) (((x) >> 15) & 3)
146 #define LCCR5_SOFM(ch) (1 << (ch - 1))
147 #define LCCR5_EOFM(ch) (1 << (ch + 7))
148 #define LCCR5_BSM(ch) (1 << (ch + 15))
149 #define LCCR5_IUM(ch) (1 << (ch + 23))
150 #define OVLC1_EN (1 << 31)
151 #define CCR_CEN (1 << 31)
152 #define FBR_BRA (1 << 0)
153 #define FBR_BINT (1 << 1)
154 #define FBR_SRCADDR (0xfffffff << 4)
155 #define LCSR0_LDD (1 << 0)
156 #define LCSR0_SOF0 (1 << 1)
157 #define LCSR0_BER (1 << 2)
158 #define LCSR0_ABC (1 << 3)
159 #define LCSR0_IU0 (1 << 4)
160 #define LCSR0_IU1 (1 << 5)
161 #define LCSR0_OU (1 << 6)
162 #define LCSR0_QD (1 << 7)
163 #define LCSR0_EOF0 (1 << 8)
164 #define LCSR0_BS0 (1 << 9)
165 #define LCSR0_SINT (1 << 10)
166 #define LCSR0_RDST (1 << 11)
167 #define LCSR0_CMDINT (1 << 12)
168 #define LCSR0_BERCH(x) (((x) & 7) << 28)
169 #define LCSR1_SOF(ch) (1 << (ch - 1))
170 #define LCSR1_EOF(ch) (1 << (ch + 7))
171 #define LCSR1_BS(ch) (1 << (ch + 15))
172 #define LCSR1_IU(ch) (1 << (ch + 23))
173 #define LDCMD_LENGTH(x) ((x) & 0x001ffffc)
174 #define LDCMD_EOFINT (1 << 21)
175 #define LDCMD_SOFINT (1 << 22)
176 #define LDCMD_PAL (1 << 26)
178 /* Route internal interrupt lines to the global IC */
179 static void pxa2xx_lcdc_int_update(struct pxa2xx_lcdc_s *s)
182 level |= (s->status[0] & LCSR0_LDD) && !(s->control[0] & LCCR0_LDM);
183 level |= (s->status[0] & LCSR0_SOF0) && !(s->control[0] & LCCR0_SOFM0);
184 level |= (s->status[0] & LCSR0_IU0) && !(s->control[0] & LCCR0_IUM);
185 level |= (s->status[0] & LCSR0_IU1) && !(s->control[5] & LCCR5_IUM(1));
186 level |= (s->status[0] & LCSR0_OU) && !(s->control[0] & LCCR0_OUM);
187 level |= (s->status[0] & LCSR0_QD) && !(s->control[0] & LCCR0_QDM);
188 level |= (s->status[0] & LCSR0_EOF0) && !(s->control[0] & LCCR0_EOFM0);
189 level |= (s->status[0] & LCSR0_BS0) && !(s->control[0] & LCCR0_BSM0);
190 level |= (s->status[0] & LCSR0_RDST) && !(s->control[0] & LCCR0_RDSTM);
191 level |= (s->status[0] & LCSR0_CMDINT) && !(s->control[0] & LCCR0_CMDIM);
192 level |= (s->status[1] & ~s->control[5]);
194 qemu_set_irq(s->irq, !!level);
198 /* Set Branch Status interrupt high and poke associated registers */
199 static inline void pxa2xx_dma_bs_set(struct pxa2xx_lcdc_s *s, int ch)
203 s->status[0] |= LCSR0_BS0;
204 unmasked = !(s->control[0] & LCCR0_BSM0);
206 s->status[1] |= LCSR1_BS(ch);
207 unmasked = !(s->control[5] & LCCR5_BSM(ch));
212 s->status[0] |= LCSR0_SINT;
214 s->liidr = s->dma_ch[ch].id;
218 /* Set Start Of Frame Status interrupt high and poke associated registers */
219 static inline void pxa2xx_dma_sof_set(struct pxa2xx_lcdc_s *s, int ch)
222 if (!(s->dma_ch[ch].command & LDCMD_SOFINT))
226 s->status[0] |= LCSR0_SOF0;
227 unmasked = !(s->control[0] & LCCR0_SOFM0);
229 s->status[1] |= LCSR1_SOF(ch);
230 unmasked = !(s->control[5] & LCCR5_SOFM(ch));
235 s->status[0] |= LCSR0_SINT;
237 s->liidr = s->dma_ch[ch].id;
241 /* Set End Of Frame Status interrupt high and poke associated registers */
242 static inline void pxa2xx_dma_eof_set(struct pxa2xx_lcdc_s *s, int ch)
245 if (!(s->dma_ch[ch].command & LDCMD_EOFINT))
249 s->status[0] |= LCSR0_EOF0;
250 unmasked = !(s->control[0] & LCCR0_EOFM0);
252 s->status[1] |= LCSR1_EOF(ch);
253 unmasked = !(s->control[5] & LCCR5_EOFM(ch));
258 s->status[0] |= LCSR0_SINT;
260 s->liidr = s->dma_ch[ch].id;
264 /* Set Bus Error Status interrupt high and poke associated registers */
265 static inline void pxa2xx_dma_ber_set(struct pxa2xx_lcdc_s *s, int ch)
267 s->status[0] |= LCSR0_BERCH(ch) | LCSR0_BER;
269 s->status[0] |= LCSR0_SINT;
271 s->liidr = s->dma_ch[ch].id;
274 /* Set Read Status interrupt high and poke associated registers */
275 static inline void pxa2xx_dma_rdst_set(struct pxa2xx_lcdc_s *s)
277 s->status[0] |= LCSR0_RDST;
278 if (s->irqlevel && !(s->control[0] & LCCR0_RDSTM))
279 s->status[0] |= LCSR0_SINT;
282 /* Load new Frame Descriptors from DMA */
283 static void pxa2xx_descriptor_load(struct pxa2xx_lcdc_s *s)
285 struct pxa_frame_descriptor_s *desc[PXA_LCDDMA_CHANS];
286 target_phys_addr_t descptr;
289 for (i = 0; i < PXA_LCDDMA_CHANS; i ++) {
291 s->dma_ch[i].source = 0;
293 if (!s->dma_ch[i].up)
296 if (s->dma_ch[i].branch & FBR_BRA) {
297 descptr = s->dma_ch[i].branch & FBR_SRCADDR;
298 if (s->dma_ch[i].branch & FBR_BINT)
299 pxa2xx_dma_bs_set(s, i);
300 s->dma_ch[i].branch &= ~FBR_BRA;
302 descptr = s->dma_ch[i].descriptor;
304 if (!(descptr >= PXA2XX_SDRAM_BASE && descptr +
305 sizeof(*desc[i]) <= PXA2XX_SDRAM_BASE + phys_ram_size))
308 descptr -= PXA2XX_SDRAM_BASE;
309 desc[i] = (struct pxa_frame_descriptor_s *) (phys_ram_base + descptr);
310 s->dma_ch[i].descriptor = desc[i]->fdaddr;
311 s->dma_ch[i].source = desc[i]->fsaddr;
312 s->dma_ch[i].id = desc[i]->fidr;
313 s->dma_ch[i].command = desc[i]->ldcmd;
317 static uint32_t pxa2xx_lcdc_read(void *opaque, target_phys_addr_t offset)
319 struct pxa2xx_lcdc_s *s = (struct pxa2xx_lcdc_s *) opaque;
325 return s->control[0];
327 return s->control[1];
329 return s->control[2];
331 return s->control[3];
333 return s->control[4];
335 return s->control[5];
357 case 0x200 ... 0x1000: /* DMA per-channel registers */
358 ch = (offset - 0x200) >> 4;
359 if (!(ch >= 0 && ch < PXA_LCDDMA_CHANS))
362 switch (offset & 0xf) {
364 return s->dma_ch[ch].descriptor;
366 return s->dma_ch[ch].source;
368 return s->dma_ch[ch].id;
370 return s->dma_ch[ch].command;
376 return s->dma_ch[0].branch;
378 return s->dma_ch[1].branch;
380 return s->dma_ch[2].branch;
382 return s->dma_ch[3].branch;
384 return s->dma_ch[4].branch;
386 return s->dma_ch[5].branch;
388 return s->dma_ch[6].branch;
405 cpu_abort(cpu_single_env,
406 "%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
412 static void pxa2xx_lcdc_write(void *opaque,
413 target_phys_addr_t offset, uint32_t value)
415 struct pxa2xx_lcdc_s *s = (struct pxa2xx_lcdc_s *) opaque;
421 /* ACK Quick Disable done */
422 if ((s->control[0] & LCCR0_ENB) && !(value & LCCR0_ENB))
423 s->status[0] |= LCSR0_QD;
425 if (!(s->control[0] & LCCR0_LCDT) && (value & LCCR0_LCDT))
426 printf("%s: internal frame buffer unsupported\n", __FUNCTION__);
428 if ((s->control[3] & LCCR3_API) &&
429 (value & LCCR0_ENB) && !(value & LCCR0_LCDT))
430 s->status[0] |= LCSR0_ABC;
432 s->control[0] = value & 0x07ffffff;
433 pxa2xx_lcdc_int_update(s);
435 s->dma_ch[0].up = !!(value & LCCR0_ENB);
436 s->dma_ch[1].up = (s->ovl1c[0] & OVLC1_EN) || (value & LCCR0_SDS);
440 s->control[1] = value;
444 s->control[2] = value;
448 s->control[3] = value & 0xefffffff;
449 s->bpp = LCCR3_BPP(value);
453 s->control[4] = value & 0x83ff81ff;
457 s->control[5] = value & 0x3f3f3f3f;
461 if (!(s->ovl1c[0] & OVLC1_EN) && (value & OVLC1_EN))
462 printf("%s: Overlay 1 not supported\n", __FUNCTION__);
464 s->ovl1c[0] = value & 0x80ffffff;
465 s->dma_ch[1].up = (value & OVLC1_EN) || (s->control[0] & LCCR0_SDS);
469 s->ovl1c[1] = value & 0x000fffff;
473 if (!(s->ovl2c[0] & OVLC1_EN) && (value & OVLC1_EN))
474 printf("%s: Overlay 2 not supported\n", __FUNCTION__);
476 s->ovl2c[0] = value & 0x80ffffff;
477 s->dma_ch[2].up = !!(value & OVLC1_EN);
478 s->dma_ch[3].up = !!(value & OVLC1_EN);
479 s->dma_ch[4].up = !!(value & OVLC1_EN);
483 s->ovl2c[1] = value & 0x007fffff;
487 if (!(s->ccr & CCR_CEN) && (value & CCR_CEN))
488 printf("%s: Hardware cursor unimplemented\n", __FUNCTION__);
490 s->ccr = value & 0x81ffffe7;
491 s->dma_ch[5].up = !!(value & CCR_CEN);
495 s->cmdcr = value & 0xff;
499 s->trgbr = value & 0x00ffffff;
503 s->tcr = value & 0x7fff;
506 case 0x200 ... 0x1000: /* DMA per-channel registers */
507 ch = (offset - 0x200) >> 4;
508 if (!(ch >= 0 && ch < PXA_LCDDMA_CHANS))
511 switch (offset & 0xf) {
513 s->dma_ch[ch].descriptor = value & 0xfffffff0;
522 s->dma_ch[0].branch = value & 0xfffffff3;
525 s->dma_ch[1].branch = value & 0xfffffff3;
528 s->dma_ch[2].branch = value & 0xfffffff3;
531 s->dma_ch[3].branch = value & 0xfffffff3;
534 s->dma_ch[4].branch = value & 0xfffffff3;
537 s->dma_ch[5].branch = value & 0xfffffff3;
540 s->dma_ch[6].branch = value & 0xfffffff3;
544 s->bscntr = value & 0xf;
551 s->status[0] &= ~(value & 0xfff);
552 if (value & LCSR0_BER)
553 s->status[0] &= ~LCSR0_BERCH(7);
557 s->status[1] &= ~(value & 0x3e3f3f);
562 cpu_abort(cpu_single_env,
563 "%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
567 static CPUReadMemoryFunc *pxa2xx_lcdc_readfn[] = {
573 static CPUWriteMemoryFunc *pxa2xx_lcdc_writefn[] = {
579 /* Load new palette for a given DMA channel, convert to internal format */
580 static void pxa2xx_palette_parse(struct pxa2xx_lcdc_s *s, int ch, int bpp)
582 int i, n, format, r, g, b, alpha;
583 uint32_t *dest, *src;
584 s->pal_for = LCCR4_PALFOR(s->control[4]);
602 src = (uint32_t *) s->dma_ch[ch].pbuffer;
603 dest = (uint32_t *) s->dma_ch[ch].palette;
604 alpha = r = g = b = 0;
606 for (i = 0; i < n; i ++) {
608 case 0: /* 16 bpp, no transparency */
610 if (s->control[0] & LCCR0_CMS)
611 r = g = b = *src & 0xff;
613 r = (*src & 0xf800) >> 8;
614 g = (*src & 0x07e0) >> 3;
615 b = (*src & 0x001f) << 3;
618 case 1: /* 16 bpp plus transparency */
619 alpha = *src & (1 << 24);
620 if (s->control[0] & LCCR0_CMS)
621 r = g = b = *src & 0xff;
623 r = (*src & 0xf800) >> 8;
624 g = (*src & 0x07e0) >> 3;
625 b = (*src & 0x001f) << 3;
628 case 2: /* 18 bpp plus transparency */
629 alpha = *src & (1 << 24);
630 if (s->control[0] & LCCR0_CMS)
631 r = g = b = *src & 0xff;
633 r = (*src & 0xf80000) >> 16;
634 g = (*src & 0x00fc00) >> 8;
635 b = (*src & 0x0000f8);
638 case 3: /* 24 bpp plus transparency */
639 alpha = *src & (1 << 24);
640 if (s->control[0] & LCCR0_CMS)
641 r = g = b = *src & 0xff;
643 r = (*src & 0xff0000) >> 16;
644 g = (*src & 0x00ff00) >> 8;
645 b = (*src & 0x0000ff);
649 switch (s->ds->depth) {
651 *dest = rgb_to_pixel8(r, g, b) | alpha;
654 *dest = rgb_to_pixel15(r, g, b) | alpha;
657 *dest = rgb_to_pixel16(r, g, b) | alpha;
660 *dest = rgb_to_pixel24(r, g, b) | alpha;
663 *dest = rgb_to_pixel32(r, g, b) | alpha;
671 static void pxa2xx_lcdc_dma0_redraw_horiz(struct pxa2xx_lcdc_s *s,
672 uint8_t *fb, int *miny, int *maxy)
674 int y, src_width, dest_width, dirty[2];
676 ram_addr_t x, addr, new_addr, start, end;
679 fn = s->line_fn[s->transp][s->bpp];
684 src_width = (s->xres + 3) & ~3; /* Pad to a 4 pixels multiple */
685 if (s->bpp == pxa_lcdc_19pbpp || s->bpp == pxa_lcdc_18pbpp)
687 else if (s->bpp > pxa_lcdc_16bpp)
689 else if (s->bpp > pxa_lcdc_8bpp)
693 dest_width = s->xres * s->dest_width;
695 addr = (ram_addr_t) (fb - phys_ram_base);
696 start = addr + s->yres * src_width;
698 dirty[0] = dirty[1] = cpu_physical_memory_get_dirty(start, VGA_DIRTY_FLAG);
699 for (y = 0; y < s->yres; y ++) {
700 new_addr = addr + src_width;
701 for (x = addr + TARGET_PAGE_SIZE; x < new_addr;
702 x += TARGET_PAGE_SIZE) {
703 dirty[1] = cpu_physical_memory_get_dirty(x, VGA_DIRTY_FLAG);
704 dirty[0] |= dirty[1];
706 if (dirty[0] || s->invalidated) {
707 fn((uint32_t *) s->dma_ch[0].palette,
708 dest, src, s->xres, s->dest_width);
724 cpu_physical_memory_reset_dirty(start, end, VGA_DIRTY_FLAG);
727 static void pxa2xx_lcdc_dma0_redraw_vert(struct pxa2xx_lcdc_s *s,
728 uint8_t *fb, int *miny, int *maxy)
730 int y, src_width, dest_width, dirty[2];
732 ram_addr_t x, addr, new_addr, start, end;
735 fn = s->line_fn[s->transp][s->bpp];
740 src_width = (s->xres + 3) & ~3; /* Pad to a 4 pixels multiple */
741 if (s->bpp == pxa_lcdc_19pbpp || s->bpp == pxa_lcdc_18pbpp)
743 else if (s->bpp > pxa_lcdc_16bpp)
745 else if (s->bpp > pxa_lcdc_8bpp)
748 dest_width = s->yres * s->dest_width;
749 dest = s->ds->data + dest_width * (s->xres - 1);
751 addr = (ram_addr_t) (fb - phys_ram_base);
752 start = addr + s->yres * src_width;
754 dirty[0] = dirty[1] = cpu_physical_memory_get_dirty(start, VGA_DIRTY_FLAG);
755 for (y = 0; y < s->yres; y ++) {
756 new_addr = addr + src_width;
757 for (x = addr + TARGET_PAGE_SIZE; x < new_addr;
758 x += TARGET_PAGE_SIZE) {
759 dirty[1] = cpu_physical_memory_get_dirty(x, VGA_DIRTY_FLAG);
760 dirty[0] |= dirty[1];
762 if (dirty[0] || s->invalidated) {
763 fn((uint32_t *) s->dma_ch[0].palette,
764 dest, src, s->xres, -dest_width);
776 dest += s->dest_width;
780 cpu_physical_memory_reset_dirty(start, end, VGA_DIRTY_FLAG);
783 static void pxa2xx_lcdc_resize(struct pxa2xx_lcdc_s *s)
786 if (!(s->control[0] & LCCR0_ENB))
789 width = LCCR1_PPL(s->control[1]) + 1;
790 height = LCCR2_LPP(s->control[2]) + 1;
792 if (width != s->xres || height != s->yres) {
794 dpy_resize(s->ds, height, width);
796 dpy_resize(s->ds, width, height);
803 static void pxa2xx_update_display(void *opaque)
805 struct pxa2xx_lcdc_s *s = (struct pxa2xx_lcdc_s *) opaque;
807 target_phys_addr_t fbptr;
810 if (!(s->control[0] & LCCR0_ENB))
813 pxa2xx_descriptor_load(s);
815 pxa2xx_lcdc_resize(s);
818 s->transp = s->dma_ch[2].up || s->dma_ch[3].up;
819 /* Note: With overlay planes the order depends on LCCR0 bit 25. */
820 for (ch = 0; ch < PXA_LCDDMA_CHANS; ch ++)
821 if (s->dma_ch[ch].up) {
822 if (!s->dma_ch[ch].source) {
823 pxa2xx_dma_ber_set(s, ch);
826 fbptr = s->dma_ch[ch].source;
827 if (!(fbptr >= PXA2XX_SDRAM_BASE &&
828 fbptr <= PXA2XX_SDRAM_BASE + phys_ram_size)) {
829 pxa2xx_dma_ber_set(s, ch);
832 fbptr -= PXA2XX_SDRAM_BASE;
833 fb = phys_ram_base + fbptr;
835 if (s->dma_ch[ch].command & LDCMD_PAL) {
836 memcpy(s->dma_ch[ch].pbuffer, fb,
837 MAX(LDCMD_LENGTH(s->dma_ch[ch].command),
838 sizeof(s->dma_ch[ch].pbuffer)));
839 pxa2xx_palette_parse(s, ch, s->bpp);
841 /* Do we need to reparse palette */
842 if (LCCR4_PALFOR(s->control[4]) != s->pal_for)
843 pxa2xx_palette_parse(s, ch, s->bpp);
845 /* ACK frame start */
846 pxa2xx_dma_sof_set(s, ch);
848 s->dma_ch[ch].redraw(s, fb, &miny, &maxy);
851 /* ACK frame completed */
852 pxa2xx_dma_eof_set(s, ch);
856 if (s->control[0] & LCCR0_DIS) {
857 /* ACK last frame completed */
858 s->control[0] &= ~LCCR0_ENB;
859 s->status[0] |= LCSR0_LDD;
863 dpy_update(s->ds, miny, 0, maxy, s->xres);
865 dpy_update(s->ds, 0, miny, s->xres, maxy);
866 pxa2xx_lcdc_int_update(s);
869 s->vsync_cb(s->opaque);
872 static void pxa2xx_invalidate_display(void *opaque)
874 struct pxa2xx_lcdc_s *s = (struct pxa2xx_lcdc_s *) opaque;
878 static void pxa2xx_screen_dump(void *opaque, const char *filename)
883 void pxa2xx_lcdc_orientation(void *opaque, int angle)
885 struct pxa2xx_lcdc_s *s = (struct pxa2xx_lcdc_s *) opaque;
888 s->dma_ch[0].redraw = pxa2xx_lcdc_dma0_redraw_vert;
890 s->dma_ch[0].redraw = pxa2xx_lcdc_dma0_redraw_horiz;
893 s->orientation = angle;
894 s->xres = s->yres = -1;
895 pxa2xx_lcdc_resize(s);
898 static void pxa2xx_lcdc_save(QEMUFile *f, void *opaque)
900 struct pxa2xx_lcdc_s *s = (struct pxa2xx_lcdc_s *) opaque;
903 qemu_put_be32(f, s->irqlevel);
904 qemu_put_be32(f, s->transp);
906 for (i = 0; i < 6; i ++)
907 qemu_put_be32s(f, &s->control[i]);
908 for (i = 0; i < 2; i ++)
909 qemu_put_be32s(f, &s->status[i]);
910 for (i = 0; i < 2; i ++)
911 qemu_put_be32s(f, &s->ovl1c[i]);
912 for (i = 0; i < 2; i ++)
913 qemu_put_be32s(f, &s->ovl2c[i]);
914 qemu_put_be32s(f, &s->ccr);
915 qemu_put_be32s(f, &s->cmdcr);
916 qemu_put_be32s(f, &s->trgbr);
917 qemu_put_be32s(f, &s->tcr);
918 qemu_put_be32s(f, &s->liidr);
919 qemu_put_8s(f, &s->bscntr);
921 for (i = 0; i < 7; i ++) {
922 qemu_put_betl(f, s->dma_ch[i].branch);
923 qemu_put_byte(f, s->dma_ch[i].up);
924 qemu_put_buffer(f, s->dma_ch[i].pbuffer, sizeof(s->dma_ch[i].pbuffer));
926 qemu_put_betl(f, s->dma_ch[i].descriptor);
927 qemu_put_betl(f, s->dma_ch[i].source);
928 qemu_put_be32s(f, &s->dma_ch[i].id);
929 qemu_put_be32s(f, &s->dma_ch[i].command);
933 static int pxa2xx_lcdc_load(QEMUFile *f, void *opaque, int version_id)
935 struct pxa2xx_lcdc_s *s = (struct pxa2xx_lcdc_s *) opaque;
938 s->irqlevel = qemu_get_be32(f);
939 s->transp = qemu_get_be32(f);
941 for (i = 0; i < 6; i ++)
942 qemu_get_be32s(f, &s->control[i]);
943 for (i = 0; i < 2; i ++)
944 qemu_get_be32s(f, &s->status[i]);
945 for (i = 0; i < 2; i ++)
946 qemu_get_be32s(f, &s->ovl1c[i]);
947 for (i = 0; i < 2; i ++)
948 qemu_get_be32s(f, &s->ovl2c[i]);
949 qemu_get_be32s(f, &s->ccr);
950 qemu_get_be32s(f, &s->cmdcr);
951 qemu_get_be32s(f, &s->trgbr);
952 qemu_get_be32s(f, &s->tcr);
953 qemu_get_be32s(f, &s->liidr);
954 qemu_get_8s(f, &s->bscntr);
956 for (i = 0; i < 7; i ++) {
957 s->dma_ch[i].branch = qemu_get_betl(f);
958 s->dma_ch[i].up = qemu_get_byte(f);
959 qemu_get_buffer(f, s->dma_ch[i].pbuffer, sizeof(s->dma_ch[i].pbuffer));
961 s->dma_ch[i].descriptor = qemu_get_betl(f);
962 s->dma_ch[i].source = qemu_get_betl(f);
963 qemu_get_be32s(f, &s->dma_ch[i].id);
964 qemu_get_be32s(f, &s->dma_ch[i].command);
967 s->bpp = LCCR3_BPP(s->control[3]);
968 s->xres = s->yres = s->pal_for = -1;
974 #include "pxa2xx_template.h"
976 #include "pxa2xx_template.h"
978 #include "pxa2xx_template.h"
980 #include "pxa2xx_template.h"
982 #include "pxa2xx_template.h"
984 struct pxa2xx_lcdc_s *pxa2xx_lcdc_init(target_phys_addr_t base, qemu_irq irq,
988 struct pxa2xx_lcdc_s *s;
990 s = (struct pxa2xx_lcdc_s *) qemu_mallocz(sizeof(struct pxa2xx_lcdc_s));
996 pxa2xx_lcdc_orientation(s, graphic_rotate);
998 iomemtype = cpu_register_io_memory(0, pxa2xx_lcdc_readfn,
999 pxa2xx_lcdc_writefn, s);
1000 cpu_register_physical_memory(base, 0x00100000, iomemtype);
1002 graphic_console_init(ds, pxa2xx_update_display,
1003 pxa2xx_invalidate_display, pxa2xx_screen_dump, s);
1005 switch (s->ds->depth) {
1010 s->line_fn[0] = pxa2xx_draw_fn_8;
1011 s->line_fn[1] = pxa2xx_draw_fn_8t;
1015 s->line_fn[0] = pxa2xx_draw_fn_15;
1016 s->line_fn[1] = pxa2xx_draw_fn_15t;
1020 s->line_fn[0] = pxa2xx_draw_fn_16;
1021 s->line_fn[1] = pxa2xx_draw_fn_16t;
1025 s->line_fn[0] = pxa2xx_draw_fn_24;
1026 s->line_fn[1] = pxa2xx_draw_fn_24t;
1030 s->line_fn[0] = pxa2xx_draw_fn_32;
1031 s->line_fn[1] = pxa2xx_draw_fn_32t;
1035 fprintf(stderr, "%s: Bad color depth\n", __FUNCTION__);
1039 register_savevm("pxa2xx_lcdc", 0, 0,
1040 pxa2xx_lcdc_save, pxa2xx_lcdc_load, s);
1045 void pxa2xx_lcd_vsync_cb(struct pxa2xx_lcdc_s *s,
1046 void (*cb)(void *opaque), void *opaque) {