2 * Intel XScale PXA255/270 processor support.
4 * Copyright (c) 2006 Openedhand Ltd.
5 * Written by Andrzej Zaborowski <balrog@zabor.org>
7 * This code is licenced under the GPL.
10 # define PXA_H "pxa.h"
12 /* Interrupt numbers */
13 # define PXA2XX_PIC_SSP3 0
14 # define PXA2XX_PIC_USBH2 2
15 # define PXA2XX_PIC_USBH1 3
16 # define PXA2XX_PIC_PWRI2C 6
17 # define PXA25X_PIC_HWUART 7
18 # define PXA27X_PIC_OST_4_11 7
19 # define PXA2XX_PIC_GPIO_0 8
20 # define PXA2XX_PIC_GPIO_1 9
21 # define PXA2XX_PIC_GPIO_X 10
22 # define PXA2XX_PIC_I2S 13
23 # define PXA26X_PIC_ASSP 15
24 # define PXA25X_PIC_NSSP 16
25 # define PXA27X_PIC_SSP2 16
26 # define PXA2XX_PIC_LCD 17
27 # define PXA2XX_PIC_I2C 18
28 # define PXA2XX_PIC_ICP 19
29 # define PXA2XX_PIC_STUART 20
30 # define PXA2XX_PIC_BTUART 21
31 # define PXA2XX_PIC_FFUART 22
32 # define PXA2XX_PIC_MMC 23
33 # define PXA2XX_PIC_SSP 24
34 # define PXA2XX_PIC_DMA 25
35 # define PXA2XX_PIC_OST_0 26
36 # define PXA2XX_PIC_RTC1HZ 30
37 # define PXA2XX_PIC_RTCALARM 31
40 # define PXA2XX_RX_RQ_I2S 2
41 # define PXA2XX_TX_RQ_I2S 3
42 # define PXA2XX_RX_RQ_BTUART 4
43 # define PXA2XX_TX_RQ_BTUART 5
44 # define PXA2XX_RX_RQ_FFUART 6
45 # define PXA2XX_TX_RQ_FFUART 7
46 # define PXA2XX_RX_RQ_SSP1 13
47 # define PXA2XX_TX_RQ_SSP1 14
48 # define PXA2XX_RX_RQ_SSP2 15
49 # define PXA2XX_TX_RQ_SSP2 16
50 # define PXA2XX_RX_RQ_ICP 17
51 # define PXA2XX_TX_RQ_ICP 18
52 # define PXA2XX_RX_RQ_STUART 19
53 # define PXA2XX_TX_RQ_STUART 20
54 # define PXA2XX_RX_RQ_MMCI 21
55 # define PXA2XX_TX_RQ_MMCI 22
56 # define PXA2XX_USB_RQ(x) ((x) + 24)
57 # define PXA2XX_RX_RQ_SSP3 66
58 # define PXA2XX_TX_RQ_SSP3 67
60 # define PXA2XX_SDRAM_BASE 0xa0000000
61 # define PXA2XX_INTERNAL_BASE 0x5c000000
62 # define PXA2XX_INTERNAL_SIZE 0x40000
65 qemu_irq *pxa2xx_pic_init(target_phys_addr_t base, CPUState *env);
68 void pxa25x_timer_init(target_phys_addr_t base,
69 qemu_irq *irqs, CPUState *cpustate);
70 void pxa27x_timer_init(target_phys_addr_t base,
71 qemu_irq *irqs, qemu_irq irq4, CPUState *cpustate);
74 struct pxa2xx_gpio_info_s;
75 struct pxa2xx_gpio_info_s *pxa2xx_gpio_init(target_phys_addr_t base,
76 CPUState *env, qemu_irq *pic, int lines);
77 void pxa2xx_gpio_set(struct pxa2xx_gpio_info_s *s, int line, int level);
78 void pxa2xx_gpio_handler_set(struct pxa2xx_gpio_info_s *s, int line,
79 gpio_handler_t handler, void *opaque);
80 void pxa2xx_gpio_read_notifier(struct pxa2xx_gpio_info_s *s,
81 void (*handler)(void *opaque), void *opaque);
84 struct pxa2xx_dma_state_s;
85 struct pxa2xx_dma_state_s *pxa255_dma_init(target_phys_addr_t base,
87 struct pxa2xx_dma_state_s *pxa27x_dma_init(target_phys_addr_t base,
89 void pxa2xx_dma_request(struct pxa2xx_dma_state_s *s, int req_num, int on);
93 struct pxa2xx_lcdc_s *pxa2xx_lcdc_init(target_phys_addr_t base,
94 qemu_irq irq, DisplayState *ds);
95 void pxa2xx_lcd_vsync_cb(struct pxa2xx_lcdc_s *s,
96 void (*cb)(void *opaque), void *opaque);
97 void pxa2xx_lcdc_oritentation(void *opaque, int angle);
100 struct pxa2xx_mmci_s;
101 struct pxa2xx_mmci_s *pxa2xx_mmci_init(target_phys_addr_t base,
102 qemu_irq irq, void *dma);
103 void pxa2xx_mmci_handlers(struct pxa2xx_mmci_s *s, void *opaque,
104 void (*readonly_cb)(void *, int),
105 void (*coverswitch_cb)(void *, int));
107 /* pxa2xx_pcmcia.c */
108 struct pxa2xx_pcmcia_s;
109 struct pxa2xx_pcmcia_s *pxa2xx_pcmcia_init(target_phys_addr_t base);
110 int pxa2xx_pcmcia_attach(void *opaque, struct pcmcia_card_s *card);
111 int pxa2xx_pcmcia_dettach(void *opaque);
112 void pxa2xx_pcmcia_set_irq_cb(void *opaque, qemu_irq irq, qemu_irq cd_irq);
116 void pxa2xx_ssp_attach(struct pxa2xx_ssp_s *port,
117 uint32_t (*readfn)(void *opaque),
118 void (*writefn)(void *opaque, uint32_t value), void *opaque);
123 struct pxa2xx_state_s {
126 struct pxa2xx_dma_state_s *dma;
127 struct pxa2xx_gpio_info_s *gpio;
128 struct pxa2xx_lcdc_s *lcd;
129 struct pxa2xx_ssp_s **ssp;
130 struct pxa2xx_mmci_s *mmc;
131 struct pxa2xx_pcmcia_s *pcmcia[2];
132 struct pxa2xx_i2s_s *i2s;
133 struct pxa2xx_fir_s *fir;
135 /* Power management */
136 target_phys_addr_t pm_base;
137 uint32_t pm_regs[0x40];
139 /* Clock management */
140 target_phys_addr_t cm_base;
144 /* Memory management */
145 target_phys_addr_t mm_base;
146 uint32_t mm_regs[0x1a];
148 /* Performance monitoring */
151 /* Real-Time clock */
152 target_phys_addr_t rtc_base;
167 uint32_t last_rtcpicr;
172 QEMUTimer *rtc_rdal1;
173 QEMUTimer *rtc_rdal2;
174 QEMUTimer *rtc_swal1;
175 QEMUTimer *rtc_swal2;
179 struct pxa2xx_i2s_s {
180 target_phys_addr_t base;
182 struct pxa2xx_dma_state_s *dma;
183 void (*data_req)(void *, int, int);
193 void (*codec_out)(void *, uint32_t);
194 uint32_t (*codec_in)(void *);
201 # define PA_FMT "0x%08lx"
202 # define REG_FMT "0x%lx"
204 struct pxa2xx_state_s *pxa270_init(unsigned int sdram_size, DisplayState *ds,
205 const char *revision);
206 struct pxa2xx_state_s *pxa255_init(unsigned int sdram_size, DisplayState *ds);
208 void pxa2xx_reset(int line, int level, void *opaque);