4 * Copyright (c) 2006 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 typedef uint32_t pci_addr_t;
29 typedef PCIHostState PREPPCIState;
31 static void pci_prep_addr_writel(void* opaque, uint32_t addr, uint32_t val)
33 PREPPCIState *s = opaque;
37 static uint32_t pci_prep_addr_readl(void* opaque, uint32_t addr)
39 PREPPCIState *s = opaque;
43 static inline uint32_t PPC_PCIIO_config(target_phys_addr_t addr)
47 for(i = 0; i < 11; i++) {
48 if ((addr & (1 << (11 + i))) != 0)
51 return (addr & 0x7ff) | (i << 11);
54 static void PPC_PCIIO_writeb (void *opaque, target_phys_addr_t addr, uint32_t val)
56 PREPPCIState *s = opaque;
57 pci_data_write(s->bus, PPC_PCIIO_config(addr), val, 1);
60 static void PPC_PCIIO_writew (void *opaque, target_phys_addr_t addr, uint32_t val)
62 PREPPCIState *s = opaque;
63 #ifdef TARGET_WORDS_BIGENDIAN
66 pci_data_write(s->bus, PPC_PCIIO_config(addr), val, 2);
69 static void PPC_PCIIO_writel (void *opaque, target_phys_addr_t addr, uint32_t val)
71 PREPPCIState *s = opaque;
72 #ifdef TARGET_WORDS_BIGENDIAN
75 pci_data_write(s->bus, PPC_PCIIO_config(addr), val, 4);
78 static uint32_t PPC_PCIIO_readb (void *opaque, target_phys_addr_t addr)
80 PREPPCIState *s = opaque;
82 val = pci_data_read(s->bus, PPC_PCIIO_config(addr), 1);
86 static uint32_t PPC_PCIIO_readw (void *opaque, target_phys_addr_t addr)
88 PREPPCIState *s = opaque;
90 val = pci_data_read(s->bus, PPC_PCIIO_config(addr), 2);
91 #ifdef TARGET_WORDS_BIGENDIAN
97 static uint32_t PPC_PCIIO_readl (void *opaque, target_phys_addr_t addr)
99 PREPPCIState *s = opaque;
101 val = pci_data_read(s->bus, PPC_PCIIO_config(addr), 4);
102 #ifdef TARGET_WORDS_BIGENDIAN
108 static CPUWriteMemoryFunc *PPC_PCIIO_write[] = {
114 static CPUReadMemoryFunc *PPC_PCIIO_read[] = {
120 /* Don't know if this matches real hardware, but it agrees with OHW. */
121 static int prep_map_irq(PCIDevice *pci_dev, int irq_num)
123 return (irq_num + (pci_dev->devfn >> 3)) & 3;
126 static int prep_irq_levels[4];
128 static void prep_set_irq(void *pic, int irq_num, int level)
131 prep_irq_levels[irq_num] = level;
132 level |= prep_irq_levels[irq_num ^ 2];
133 pic_irq_num = (irq_num == 0 || irq_num == 2) ? 9 : 11;
134 pic_set_irq(pic_irq_num, level);
137 PCIBus *pci_prep_init(void)
143 s = qemu_mallocz(sizeof(PREPPCIState));
144 s->bus = pci_register_bus(prep_set_irq, prep_map_irq, NULL, 0);
146 register_ioport_write(0xcf8, 4, 4, pci_prep_addr_writel, s);
147 register_ioport_read(0xcf8, 4, 4, pci_prep_addr_readl, s);
149 register_ioport_write(0xcfc, 4, 1, pci_host_data_writeb, s);
150 register_ioport_write(0xcfc, 4, 2, pci_host_data_writew, s);
151 register_ioport_write(0xcfc, 4, 4, pci_host_data_writel, s);
152 register_ioport_read(0xcfc, 4, 1, pci_host_data_readb, s);
153 register_ioport_read(0xcfc, 4, 2, pci_host_data_readw, s);
154 register_ioport_read(0xcfc, 4, 4, pci_host_data_readl, s);
156 PPC_io_memory = cpu_register_io_memory(0, PPC_PCIIO_read,
158 cpu_register_physical_memory(0x80800000, 0x00400000, PPC_io_memory);
160 /* PCI host bridge */
161 d = pci_register_device(s->bus, "PREP Host Bridge - Motorola Raven",
162 sizeof(PCIDevice), 0, NULL, NULL);
163 d->config[0x00] = 0x57; // vendor_id : Motorola
164 d->config[0x01] = 0x10;
165 d->config[0x02] = 0x01; // device_id : Raven
166 d->config[0x03] = 0x48;
167 d->config[0x08] = 0x00; // revision
168 d->config[0x0A] = 0x00; // class_sub = pci host
169 d->config[0x0B] = 0x06; // class_base = PCI_bridge
170 d->config[0x0C] = 0x08; // cache_line_size
171 d->config[0x0D] = 0x10; // latency_timer
172 d->config[0x0E] = 0x00; // header_type
173 d->config[0x34] = 0x00; // capabilities_pointer