94a83d7179853be125db236b514e23ebec31bdbe
[qemu] / hw / ppce500_mpc8544ds.c
1 /*
2  * Qemu PowerPC MPC8544DS board emualtion
3  *
4  * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved.
5  *
6  * Author: Yu Liu,     <yu.liu@freescale.com>
7  *
8  * This file is derived from hw/ppc440_bamboo.c,
9  * the copyright for that material belongs to the original owners.
10  *
11  * This is free software; you can redistribute it and/or modify
12  * it under the terms of  the GNU General  Public License as published by
13  * the Free Software Foundation;  either version 2 of the  License, or
14  * (at your option) any later version.
15  */
16
17 #include <dirent.h>
18
19 #include "config.h"
20 #include "qemu-common.h"
21 #include "net.h"
22 #include "hw.h"
23 #include "pc.h"
24 #include "pci.h"
25 #include "virtio-blk.h"
26 #include "boards.h"
27 #include "sysemu.h"
28 #include "kvm.h"
29 #include "kvm_ppc.h"
30 #include "device_tree.h"
31 #include "openpic.h"
32 #include "ppce500.h"
33
34 #define BINARY_DEVICE_TREE_FILE    "mpc8544ds.dtb"
35 #define UIMAGE_LOAD_BASE           0
36 #define DTB_LOAD_BASE              0x600000
37 #define INITRD_LOAD_BASE           0x2000000
38
39 #define RAM_SIZES_ALIGN            (64UL << 20)
40
41 #define MPC8544_CCSRBAR_BASE       0xE0000000
42 #define MPC8544_MPIC_REGS_BASE     (MPC8544_CCSRBAR_BASE + 0x40000)
43 #define MPC8544_SERIAL0_REGS_BASE  (MPC8544_CCSRBAR_BASE + 0x4500)
44 #define MPC8544_SERIAL1_REGS_BASE  (MPC8544_CCSRBAR_BASE + 0x4600)
45 #define MPC8544_PCI_REGS_BASE      (MPC8544_CCSRBAR_BASE + 0x8000)
46 #define MPC8544_PCI_REGS_SIZE      0x1000
47 #define MPC8544_PCI_IO             0xE1000000
48 #define MPC8544_PCI_IOLEN          0x10000
49
50 #ifdef HAVE_FDT
51 static int mpc8544_copy_soc_cell(void *fdt, const char *node, const char *prop)
52 {
53     uint32_t cell;
54     int ret;
55
56     ret = kvmppc_read_host_property(node, prop, &cell, sizeof(cell));
57     if (ret < 0) {
58         fprintf(stderr, "couldn't read host %s/%s\n", node, prop);
59         goto out;
60     }
61
62     ret = qemu_devtree_setprop_cell(fdt, "/cpus/PowerPC,8544@0",
63                                 prop, cell);
64     if (ret < 0) {
65         fprintf(stderr, "couldn't set guest /cpus/PowerPC,8544@0/%s\n", prop);
66         goto out;
67     }
68
69 out:
70     return ret;
71 }
72 #endif
73
74 static void *mpc8544_load_device_tree(target_phys_addr_t addr,
75                                      uint32_t ramsize,
76                                      target_phys_addr_t initrd_base,
77                                      target_phys_addr_t initrd_size,
78                                      const char *kernel_cmdline)
79 {
80     void *fdt = NULL;
81 #ifdef HAVE_FDT
82     uint32_t mem_reg_property[] = {0, ramsize};
83     char *path;
84     int fdt_size;
85     int pathlen;
86     int ret;
87
88     pathlen = snprintf(NULL, 0, "%s/%s", bios_dir, BINARY_DEVICE_TREE_FILE) + 1;
89     path = qemu_malloc(pathlen);
90
91     snprintf(path, pathlen, "%s/%s", bios_dir, BINARY_DEVICE_TREE_FILE);
92
93     fdt = load_device_tree(path, &fdt_size);
94     qemu_free(path);
95     if (fdt == NULL)
96         goto out;
97
98     /* Manipulate device tree in memory. */
99     ret = qemu_devtree_setprop(fdt, "/memory", "reg", mem_reg_property,
100                                sizeof(mem_reg_property));
101     if (ret < 0)
102         fprintf(stderr, "couldn't set /memory/reg\n");
103
104     ret = qemu_devtree_setprop_cell(fdt, "/chosen", "linux,initrd-start",
105                                     initrd_base);
106     if (ret < 0)
107         fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n");
108
109     ret = qemu_devtree_setprop_cell(fdt, "/chosen", "linux,initrd-end",
110                                     (initrd_base + initrd_size));
111     if (ret < 0)
112         fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n");
113
114     ret = qemu_devtree_setprop_string(fdt, "/chosen", "bootargs",
115                                       kernel_cmdline);
116     if (ret < 0)
117         fprintf(stderr, "couldn't set /chosen/bootargs\n");
118
119     if (kvm_enabled()) {
120         struct dirent *dirp;
121         DIR *dp;
122         char buf[128];
123
124         if ((dp = opendir("/proc/device-tree/cpus/")) == NULL) {
125             printf("Can't open directory /proc/device-tree/cpus/\n");
126             goto out;
127         }
128
129         buf[0] = '\0';
130         while ((dirp = readdir(dp)) != NULL) {
131             if (strncmp(dirp->d_name, "PowerPC", 7) == 0) {
132                 snprintf(buf, 128, "/cpus/%s", dirp->d_name);
133                 break;
134             }
135         }
136         closedir(dp);
137         if (buf[0] == '\0') {
138             printf("Unknow host!\n");
139             goto out;
140         }
141
142         mpc8544_copy_soc_cell(fdt, buf, "clock-frequency");
143         mpc8544_copy_soc_cell(fdt, buf, "timebase-frequency");
144     }
145
146     cpu_physical_memory_write (addr, (void *)fdt, fdt_size);
147
148 out:
149 #endif
150
151     return fdt;
152 }
153
154 static void mpc8544ds_init(ram_addr_t ram_size,
155                          const char *boot_device,
156                          const char *kernel_filename,
157                          const char *kernel_cmdline,
158                          const char *initrd_filename,
159                          const char *cpu_model)
160 {
161     PCIBus *pci_bus;
162     CPUState *env;
163     uint64_t elf_entry;
164     uint64_t elf_lowaddr;
165     target_ulong entry=0;
166     target_ulong loadaddr=UIMAGE_LOAD_BASE;
167     target_long kernel_size=0;
168     target_ulong dt_base=DTB_LOAD_BASE;
169     target_ulong initrd_base=INITRD_LOAD_BASE;
170     target_long initrd_size=0;
171     void *fdt;
172     int i=0;
173     unsigned int pci_irq_nrs[4] = {1, 2, 3, 4};
174     qemu_irq *irqs, *mpic, *pci_irqs;
175     SerialState * serial[2];
176
177     /* Setup CPU */
178     env = cpu_ppc_init("e500v2_v30");
179     if (!env) {
180         fprintf(stderr, "Unable to initialize CPU!\n");
181         exit(1);
182     }
183
184     /* Fixup Memory size on a alignment boundary */
185     ram_size &= ~(RAM_SIZES_ALIGN - 1);
186
187     /* Register Memory */
188     cpu_register_physical_memory(0, ram_size, qemu_ram_alloc(ram_size));
189
190     /* MPIC */
191     irqs = qemu_mallocz(sizeof(qemu_irq) * OPENPIC_OUTPUT_NB);
192     irqs[OPENPIC_OUTPUT_INT] = ((qemu_irq *)env->irq_inputs)[PPCE500_INPUT_INT];
193     irqs[OPENPIC_OUTPUT_CINT] = ((qemu_irq *)env->irq_inputs)[PPCE500_INPUT_CINT];
194     mpic = mpic_init(MPC8544_MPIC_REGS_BASE, 1, &irqs, NULL);
195
196     /* Serial */
197     if (serial_hds[0])
198         serial[0] = serial_mm_init(MPC8544_SERIAL0_REGS_BASE,
199                                0, mpic[12+26], 399193,
200                         serial_hds[0], 1);
201
202     if (serial_hds[1])
203         serial[0] = serial_mm_init(MPC8544_SERIAL1_REGS_BASE,
204                         0, mpic[12+26], 399193,
205                         serial_hds[0], 1);
206
207     /* PCI */
208     pci_irqs = qemu_malloc(sizeof(qemu_irq) * 4);
209     pci_irqs[0] = mpic[pci_irq_nrs[0]];
210     pci_irqs[1] = mpic[pci_irq_nrs[1]];
211     pci_irqs[2] = mpic[pci_irq_nrs[2]];
212     pci_irqs[3] = mpic[pci_irq_nrs[3]];
213     pci_bus = ppce500_pci_init(pci_irqs, MPC8544_PCI_REGS_BASE);
214     if (!pci_bus)
215         printf("couldn't create PCI controller!\n");
216
217     isa_mmio_init(MPC8544_PCI_IO, MPC8544_PCI_IOLEN);
218
219     if (pci_bus) {
220         int unit_id = 0;
221
222         /* Add virtio block devices. */
223         while ((i = drive_get_index(IF_VIRTIO, 0, unit_id)) != -1) {
224             virtio_blk_init(pci_bus, drives_table[i].bdrv);
225             unit_id++;
226         }
227
228         /* Register network interfaces. */
229         for (i = 0; i < nb_nics; i++) {
230             pci_nic_init(pci_bus, &nd_table[i], -1, "virtio");
231         }
232     }
233
234     /* Load kernel. */
235     if (kernel_filename) {
236         kernel_size = load_uimage(kernel_filename, &entry, &loadaddr, NULL);
237         if (kernel_size < 0) {
238             kernel_size = load_elf(kernel_filename, 0, &elf_entry, &elf_lowaddr,
239                                    NULL);
240             entry = elf_entry;
241             loadaddr = elf_lowaddr;
242         }
243         /* XXX try again as binary */
244         if (kernel_size < 0) {
245             fprintf(stderr, "qemu: could not load kernel '%s'\n",
246                     kernel_filename);
247             exit(1);
248         }
249     }
250
251     /* Load initrd. */
252     if (initrd_filename) {
253         initrd_size = load_image_targphys(initrd_filename, initrd_base,
254                                           ram_size - initrd_base);
255
256         if (initrd_size < 0) {
257             fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
258                     initrd_filename);
259             exit(1);
260         }
261     }
262
263     /* If we're loading a kernel directly, we must load the device tree too. */
264     if (kernel_filename) {
265         fdt = mpc8544_load_device_tree(dt_base, ram_size,
266                                       initrd_base, initrd_size, kernel_cmdline);
267         if (fdt == NULL) {
268             fprintf(stderr, "couldn't load device tree\n");
269             exit(1);
270         }
271
272         /* Set initial guest state. */
273         env->gpr[1] = (16<<20) - 8;
274         env->gpr[3] = dt_base;
275         env->nip = entry;
276         /* XXX we currently depend on KVM to create some initial TLB entries. */
277     }
278
279     if (kvm_enabled())
280         kvmppc_init();
281
282     return;
283 }
284
285 QEMUMachine mpc8544ds_machine = {
286     .name = "mpc8544ds",
287     .desc = "mpc8544ds",
288     .init = mpc8544ds_init,
289 };