2 * QEMU PPC CHRP/PMAC hardware System Emulator
4 * Copyright (c) 2004-2007 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 /* SMP is not enabled, for now */
29 #define BIOS_FILENAME "ppc_rom.bin"
30 #define VGABIOS_FILENAME "video.x"
31 #define NVRAM_SIZE 0x2000
33 #define KERNEL_LOAD_ADDR 0x01000000
34 #define INITRD_LOAD_ADDR 0x01800000
36 /* MacIO devices (mapped inside the MacIO address space): CUDA, DBDMA,
39 static int dbdma_mem_index;
40 static int cuda_mem_index;
41 static int ide0_mem_index = -1;
42 static int ide1_mem_index = -1;
43 static int openpic_mem_index = -1;
44 static int heathrow_pic_mem_index = -1;
45 static int macio_nvram_mem_index = -1;
47 /* DBDMA: currently no op - should suffice right now */
49 static void dbdma_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)
51 printf("%s: 0x" PADDRX " <= 0x%08x\n", __func__, addr, value);
54 static void dbdma_writew (void *opaque, target_phys_addr_t addr, uint32_t value)
58 static void dbdma_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
62 static uint32_t dbdma_readb (void *opaque, target_phys_addr_t addr)
64 printf("%s: 0x" PADDRX " => 0x00000000\n", __func__, addr);
68 static uint32_t dbdma_readw (void *opaque, target_phys_addr_t addr)
73 static uint32_t dbdma_readl (void *opaque, target_phys_addr_t addr)
78 static CPUWriteMemoryFunc *dbdma_write[] = {
84 static CPUReadMemoryFunc *dbdma_read[] = {
90 /* macio style NVRAM device */
91 typedef struct MacIONVRAMState {
95 static void macio_nvram_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)
97 MacIONVRAMState *s = opaque;
98 addr = (addr >> 4) & 0x1fff;
99 s->data[addr] = value;
100 // printf("macio_nvram_writeb %04x = %02x\n", addr, value);
103 static uint32_t macio_nvram_readb (void *opaque, target_phys_addr_t addr)
105 MacIONVRAMState *s = opaque;
108 addr = (addr >> 4) & 0x1fff;
109 value = s->data[addr];
110 // printf("macio_nvram_readb %04x = %02x\n", addr, value);
114 static CPUWriteMemoryFunc *macio_nvram_write[] = {
120 static CPUReadMemoryFunc *macio_nvram_read[] = {
126 static MacIONVRAMState *macio_nvram_init(void)
129 s = qemu_mallocz(sizeof(MacIONVRAMState));
132 macio_nvram_mem_index = cpu_register_io_memory(0, macio_nvram_read,
133 macio_nvram_write, s);
137 static void macio_map(PCIDevice *pci_dev, int region_num,
138 uint32_t addr, uint32_t size, int type)
140 if (heathrow_pic_mem_index >= 0) {
141 cpu_register_physical_memory(addr + 0x00000, 0x1000,
142 heathrow_pic_mem_index);
144 cpu_register_physical_memory(addr + 0x08000, 0x1000, dbdma_mem_index);
145 cpu_register_physical_memory(addr + 0x16000, 0x2000, cuda_mem_index);
146 if (ide0_mem_index >= 0)
147 cpu_register_physical_memory(addr + 0x1f000, 0x1000, ide0_mem_index);
148 if (ide1_mem_index >= 0)
149 cpu_register_physical_memory(addr + 0x20000, 0x1000, ide1_mem_index);
150 if (openpic_mem_index >= 0) {
151 cpu_register_physical_memory(addr + 0x40000, 0x40000,
154 if (macio_nvram_mem_index >= 0)
155 cpu_register_physical_memory(addr + 0x60000, 0x20000, macio_nvram_mem_index);
158 static void macio_init(PCIBus *bus, int device_id)
162 d = pci_register_device(bus, "macio", sizeof(PCIDevice),
164 /* Note: this code is strongly inspirated from the corresponding code
166 d->config[0x00] = 0x6b; // vendor_id
167 d->config[0x01] = 0x10;
168 d->config[0x02] = device_id;
169 d->config[0x03] = device_id >> 8;
171 d->config[0x0a] = 0x00; // class_sub = pci2pci
172 d->config[0x0b] = 0xff; // class_base = bridge
173 d->config[0x0e] = 0x00; // header_type
175 d->config[0x3d] = 0x01; // interrupt on pin 1
177 dbdma_mem_index = cpu_register_io_memory(0, dbdma_read, dbdma_write, NULL);
179 pci_register_io_region(d, 0, 0x80000,
180 PCI_ADDRESS_SPACE_MEM, macio_map);
184 static void unin_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
188 static uint32_t unin_readl (void *opaque, target_phys_addr_t addr)
193 static CPUWriteMemoryFunc *unin_write[] = {
199 static CPUReadMemoryFunc *unin_read[] = {
205 /* temporary frame buffer OSI calls for the video.x driver. The right
206 solution is to modify the driver to use VGA PCI I/Os */
207 static int vga_osi_call(CPUState *env)
209 static int vga_vbl_enabled;
212 // printf("osi_call R5=%d\n", env->gpr[5]);
214 /* same handler as PearPC, coming from the original MOL video
216 switch(env->gpr[5]) {
219 case 28: /* set_vmode */
220 if (env->gpr[6] != 1 || env->gpr[7] != 0)
225 case 29: /* get_vmode_info */
226 if (env->gpr[6] != 0) {
227 if (env->gpr[6] != 1 || env->gpr[7] != 0) {
233 env->gpr[4] = (1 << 16) | 1; /* num_vmodes, cur_vmode */
234 env->gpr[5] = (1 << 16) | 0; /* num_depths, cur_depth_mode */
235 env->gpr[6] = (graphic_width << 16) | graphic_height; /* w, h */
236 env->gpr[7] = 85 << 16; /* refresh rate */
237 env->gpr[8] = (graphic_depth + 7) & ~7; /* depth (round to byte) */
238 linesize = ((graphic_depth + 7) >> 3) * graphic_width;
239 linesize = (linesize + 3) & ~3;
240 env->gpr[9] = (linesize << 16) | 0; /* row_bytes, offset */
242 case 31: /* set_video power */
245 case 39: /* video_ctrl */
246 if (env->gpr[6] == 0 || env->gpr[6] == 1)
247 vga_vbl_enabled = env->gpr[6];
252 case 59: /* set_color */
253 /* R6 = index, R7 = RGB */
256 case 64: /* get color */
260 case 116: /* set hwcursor */
261 /* R6 = x, R7 = y, R8 = visible, R9 = data */
264 fprintf(stderr, "unsupported OSI call R5=" REGX "\n", env->gpr[5]);
267 return 1; /* osi_call handled */
270 static uint8_t nvram_chksum(const uint8_t *buf, int n)
274 for(i = 0; i < n; i++)
276 return (sum & 0xff) + (sum >> 8);
279 /* set a free Mac OS NVRAM partition */
280 void pmac_format_nvram_partition(uint8_t *buf, int len)
282 char partition_name[12] = "wwwwwwwwwwww";
284 buf[0] = 0x7f; /* free partition magic */
285 buf[1] = 0; /* checksum */
288 memcpy(buf + 4, partition_name, 12);
289 buf[1] = nvram_chksum(buf, 16);
292 /* PowerPC CHRP hardware initialisation */
293 static void ppc_chrp_init (int ram_size, int vga_ram_size, int boot_device,
294 DisplayState *ds, const char **fd_filename,
296 const char *kernel_filename,
297 const char *kernel_cmdline,
298 const char *initrd_filename,
299 const char *cpu_model,
302 CPUState *env, *envs[MAX_CPUS];
304 qemu_irq *pic, **openpic_irqs;
308 unsigned long bios_offset, vga_bios_offset;
309 uint32_t kernel_base, kernel_size, initrd_base, initrd_size;
312 const char *arch_name;
313 int vga_bios_size, bios_size;
316 linux_boot = (kernel_filename != NULL);
320 qemu_register_reset(&cpu_ppc_reset, env);
321 register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
323 /* Default CPU is a generic 74x/75x */
324 if (cpu_model == NULL)
326 /* XXX: CPU model (or PVR) should be provided on command line */
327 // ppc_find_by_name("750gx", &def); // Linux boot OK
328 // ppc_find_by_name("750fx", &def); // Linux boot OK
329 /* Linux does not boot on 750cxe (and probably other 750cx based)
330 * because it assumes it has 8 IBAT & DBAT pairs as it only have 4.
332 ppc_find_by_name(cpu_model, &def);
334 cpu_abort(env, "Unable to find PowerPC CPU definition\n");
336 for (i = 0; i < smp_cpus; i++) {
337 cpu_ppc_register(env, def);
338 /* Set time-base frequency to 100 Mhz */
339 cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
340 env->osi_call = vga_osi_call;
345 cpu_register_physical_memory(0, ram_size, IO_MEM_RAM);
347 /* allocate and load BIOS */
348 bios_offset = ram_size + vga_ram_size;
349 snprintf(buf, sizeof(buf), "%s/%s", bios_dir, BIOS_FILENAME);
350 bios_size = load_image(buf, phys_ram_base + bios_offset);
351 if (bios_size < 0 || bios_size > BIOS_SIZE) {
352 cpu_abort(env, "qemu: could not load PowerPC bios '%s'\n", buf);
355 bios_size = (bios_size + 0xfff) & ~0xfff;
356 cpu_register_physical_memory((uint32_t)(-bios_size),
357 bios_size, bios_offset | IO_MEM_ROM);
359 /* allocate and load VGA BIOS */
360 vga_bios_offset = bios_offset + bios_size;
361 snprintf(buf, sizeof(buf), "%s/%s", bios_dir, VGABIOS_FILENAME);
362 vga_bios_size = load_image(buf, phys_ram_base + vga_bios_offset + 8);
363 if (vga_bios_size < 0) {
364 /* if no bios is present, we can still work */
365 fprintf(stderr, "qemu: warning: could not load VGA bios '%s'\n", buf);
368 /* set a specific header (XXX: find real Apple format for NDRV
370 phys_ram_base[vga_bios_offset] = 'N';
371 phys_ram_base[vga_bios_offset + 1] = 'D';
372 phys_ram_base[vga_bios_offset + 2] = 'R';
373 phys_ram_base[vga_bios_offset + 3] = 'V';
374 cpu_to_be32w((uint32_t *)(phys_ram_base + vga_bios_offset + 4),
378 vga_bios_size = (vga_bios_size + 0xfff) & ~0xfff;
381 kernel_base = KERNEL_LOAD_ADDR;
382 /* now we can load the kernel */
383 kernel_size = load_image(kernel_filename, phys_ram_base + kernel_base);
384 if (kernel_size < 0) {
385 cpu_abort(env, "qemu: could not load kernel '%s'\n",
390 if (initrd_filename) {
391 initrd_base = INITRD_LOAD_ADDR;
392 initrd_size = load_image(initrd_filename,
393 phys_ram_base + initrd_base);
394 if (initrd_size < 0) {
395 cpu_abort(env, "qemu: could not load initial ram disk '%s'\n",
412 isa_mem_base = 0x80000000;
414 /* Register 2 MB of ISA IO space */
415 isa_mmio_init(0xfe000000, 0x00200000);
417 /* init basic PC hardware */
418 if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
419 cpu_abort(env, "Only 6xx bus is supported on heathrow machine\n");
422 pic = heathrow_pic_init(&heathrow_pic_mem_index);
423 pci_bus = pci_grackle_init(0xfec00000, pic);
424 pci_vga_init(pci_bus, ds, phys_ram_base + ram_size,
425 ram_size, vga_ram_size,
426 vga_bios_offset, vga_bios_size);
428 /* XXX: suppress that */
429 dummy_irq = i8259_init(NULL);
431 /* XXX: use Mac Serial port */
432 serial_init(0x3f8, dummy_irq[4], serial_hds[0]);
434 for(i = 0; i < nb_nics; i++) {
435 if (!nd_table[i].model)
436 nd_table[i].model = "ne2k_pci";
437 pci_nic_init(pci_bus, &nd_table[i], -1);
440 pci_cmd646_ide_init(pci_bus, &bs_table[0], 0);
442 /* cuda also initialize ADB */
443 cuda_mem_index = cuda_init(pic[0x12]);
445 adb_kbd_init(&adb_bus);
446 adb_mouse_init(&adb_bus);
449 MacIONVRAMState *nvr;
450 nvr = macio_nvram_init();
451 pmac_format_nvram_partition(nvr->data, 0x2000);
454 macio_init(pci_bus, 0x0017);
456 nvram = m48t59_init(dummy_irq[8], 0xFFF04000, 0x0074, NVRAM_SIZE, 59);
458 arch_name = "HEATHROW";
460 isa_mem_base = 0x80000000;
462 /* Register 8 MB of ISA IO space */
463 isa_mmio_init(0xf2000000, 0x00800000);
466 unin_memory = cpu_register_io_memory(0, unin_read, unin_write, NULL);
467 cpu_register_physical_memory(0xf8000000, 0x00001000, unin_memory);
469 openpic_irqs = qemu_mallocz(smp_cpus * sizeof(qemu_irq *));
471 qemu_mallocz(smp_cpus * sizeof(qemu_irq) * OPENPIC_OUTPUT_NB);
472 for (i = 0; i < smp_cpus; i++) {
473 /* Mac99 IRQ connection between OpenPIC outputs pins
474 * and PowerPC input pins
476 switch (PPC_INPUT(env)) {
477 case PPC_FLAGS_INPUT_6xx:
478 openpic_irqs[i] = openpic_irqs[0] + (i * OPENPIC_OUTPUT_NB);
479 openpic_irqs[i][OPENPIC_OUTPUT_INT] =
480 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT];
481 openpic_irqs[i][OPENPIC_OUTPUT_CINT] =
482 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT];
483 openpic_irqs[i][OPENPIC_OUTPUT_MCK] =
484 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_MCP];
485 /* Not connected ? */
486 openpic_irqs[i][OPENPIC_OUTPUT_DEBUG] = NULL;
488 openpic_irqs[i][OPENPIC_OUTPUT_RESET] =
489 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_HRESET];
491 case PPC_FLAGS_INPUT_970:
492 openpic_irqs[i] = openpic_irqs[0] + (i * OPENPIC_OUTPUT_NB);
493 openpic_irqs[i][OPENPIC_OUTPUT_INT] =
494 ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_INT];
495 openpic_irqs[i][OPENPIC_OUTPUT_CINT] =
496 ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_INT];
497 openpic_irqs[i][OPENPIC_OUTPUT_MCK] =
498 ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_MCP];
499 /* Not connected ? */
500 openpic_irqs[i][OPENPIC_OUTPUT_DEBUG] = NULL;
502 openpic_irqs[i][OPENPIC_OUTPUT_RESET] =
503 ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_HRESET];
507 "Only bus model not supported on mac99 machine\n");
511 pic = openpic_init(NULL, &openpic_mem_index, smp_cpus,
513 pci_bus = pci_pmac_init(pic);
514 /* init basic PC hardware */
515 pci_vga_init(pci_bus, ds, phys_ram_base + ram_size,
516 ram_size, vga_ram_size,
517 vga_bios_offset, vga_bios_size);
519 /* XXX: suppress that */
520 dummy_irq = i8259_init(NULL);
522 /* XXX: use Mac Serial port */
523 serial_init(0x3f8, dummy_irq[4], serial_hds[0]);
524 for(i = 0; i < nb_nics; i++) {
525 if (!nd_table[i].model)
526 nd_table[i].model = "ne2k_pci";
527 pci_nic_init(pci_bus, &nd_table[i], -1);
530 ide0_mem_index = pmac_ide_init(&bs_table[0], pic[0x13]);
531 ide1_mem_index = pmac_ide_init(&bs_table[2], pic[0x14]);
533 pci_cmd646_ide_init(pci_bus, &bs_table[0], 0);
535 /* cuda also initialize ADB */
536 cuda_mem_index = cuda_init(pic[0x19]);
538 adb_kbd_init(&adb_bus);
539 adb_mouse_init(&adb_bus);
541 macio_init(pci_bus, 0x0022);
543 nvram = m48t59_init(dummy_irq[8], 0xFFF04000, 0x0074, NVRAM_SIZE, 59);
549 usb_ohci_init_pci(pci_bus, 3, -1);
552 if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8)
555 PPC_NVRAM_set_params(nvram, NVRAM_SIZE, arch_name, ram_size, boot_device,
556 kernel_base, kernel_size,
558 initrd_base, initrd_size,
559 /* XXX: need an option to load a NVRAM image */
561 graphic_width, graphic_height, graphic_depth);
562 /* No PCI init: the BIOS will do it */
564 /* Special port to get debug messages from Open-Firmware */
565 register_ioport_write(0x0F00, 4, 1, &PPC_debug_write, NULL);
568 static void ppc_core99_init (int ram_size, int vga_ram_size, int boot_device,
569 DisplayState *ds, const char **fd_filename,
571 const char *kernel_filename,
572 const char *kernel_cmdline,
573 const char *initrd_filename,
574 const char *cpu_model)
576 ppc_chrp_init(ram_size, vga_ram_size, boot_device,
577 ds, fd_filename, snapshot,
578 kernel_filename, kernel_cmdline,
579 initrd_filename, cpu_model, 0);
582 static void ppc_heathrow_init (int ram_size, int vga_ram_size, int boot_device,
583 DisplayState *ds, const char **fd_filename,
585 const char *kernel_filename,
586 const char *kernel_cmdline,
587 const char *initrd_filename,
588 const char *cpu_model)
590 ppc_chrp_init(ram_size, vga_ram_size, boot_device,
591 ds, fd_filename, snapshot,
592 kernel_filename, kernel_cmdline,
593 initrd_filename, cpu_model, 1);
596 QEMUMachine core99_machine = {
598 "Mac99 based PowerMAC",
602 QEMUMachine heathrow_machine = {
604 "Heathrow based PowerMAC",