2 * QEMU PowerPC 405 evaluation boards emulation
4 * Copyright (c) 2007 Jocelyn Mayer
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
30 #define BIOS_FILENAME "ppc405_rom.bin"
32 #define BIOS_SIZE (2048 * 1024)
34 #define KERNEL_LOAD_ADDR 0x00000000
35 #define INITRD_LOAD_ADDR 0x01800000
37 #define USE_FLASH_BIOS
39 #define DEBUG_BOARD_INIT
41 /*****************************************************************************/
42 /* PPC405EP reference board (IBM) */
43 /* Standalone board with:
45 * - SDRAM (0x00000000)
46 * - Flash (0xFFF80000)
48 * - NVRAM (0xF0000000)
51 typedef struct ref405ep_fpga_t ref405ep_fpga_t;
52 struct ref405ep_fpga_t {
58 static uint32_t ref405ep_fpga_readb (void *opaque, target_phys_addr_t addr)
60 ref405ep_fpga_t *fpga;
80 static void ref405ep_fpga_writeb (void *opaque,
81 target_phys_addr_t addr, uint32_t value)
83 ref405ep_fpga_t *fpga;
99 static uint32_t ref405ep_fpga_readw (void *opaque, target_phys_addr_t addr)
103 ret = ref405ep_fpga_readb(opaque, addr) << 8;
104 ret |= ref405ep_fpga_readb(opaque, addr + 1);
109 static void ref405ep_fpga_writew (void *opaque,
110 target_phys_addr_t addr, uint32_t value)
112 ref405ep_fpga_writeb(opaque, addr, (value >> 8) & 0xFF);
113 ref405ep_fpga_writeb(opaque, addr + 1, value & 0xFF);
116 static uint32_t ref405ep_fpga_readl (void *opaque, target_phys_addr_t addr)
120 ret = ref405ep_fpga_readb(opaque, addr) << 24;
121 ret |= ref405ep_fpga_readb(opaque, addr + 1) << 16;
122 ret |= ref405ep_fpga_readb(opaque, addr + 2) << 8;
123 ret |= ref405ep_fpga_readb(opaque, addr + 3);
128 static void ref405ep_fpga_writel (void *opaque,
129 target_phys_addr_t addr, uint32_t value)
131 ref405ep_fpga_writel(opaque, addr, (value >> 24) & 0xFF);
132 ref405ep_fpga_writel(opaque, addr + 1, (value >> 16) & 0xFF);
133 ref405ep_fpga_writel(opaque, addr + 2, (value >> 8) & 0xFF);
134 ref405ep_fpga_writeb(opaque, addr + 3, value & 0xFF);
137 static CPUReadMemoryFunc *ref405ep_fpga_read[] = {
138 &ref405ep_fpga_readb,
139 &ref405ep_fpga_readw,
140 &ref405ep_fpga_readl,
143 static CPUWriteMemoryFunc *ref405ep_fpga_write[] = {
144 &ref405ep_fpga_writeb,
145 &ref405ep_fpga_writew,
146 &ref405ep_fpga_writel,
149 static void ref405ep_fpga_reset (void *opaque)
151 ref405ep_fpga_t *fpga;
158 static void ref405ep_fpga_init (uint32_t base)
160 ref405ep_fpga_t *fpga;
163 fpga = qemu_mallocz(sizeof(ref405ep_fpga_t));
166 fpga_memory = cpu_register_io_memory(0, ref405ep_fpga_read,
167 ref405ep_fpga_write, fpga);
168 cpu_register_physical_memory(base, 0x00000100, fpga_memory);
169 ref405ep_fpga_reset(fpga);
170 qemu_register_reset(&ref405ep_fpga_reset, fpga);
174 static void ref405ep_init (int ram_size, int vga_ram_size, int boot_device,
175 DisplayState *ds, const char **fd_filename,
177 const char *kernel_filename,
178 const char *kernel_cmdline,
179 const char *initrd_filename,
180 const char *cpu_model)
186 ram_addr_t sram_offset, bios_offset, bdloc;
187 target_phys_addr_t ram_bases[2], ram_sizes[2];
188 target_ulong sram_size, bios_size;
190 //static int phy_addr = 1;
191 target_ulong kernel_base, kernel_size, initrd_base, initrd_size;
193 int fl_idx, fl_sectors, len;
196 ram_bases[0] = 0x00000000;
197 ram_sizes[0] = 0x08000000;
198 ram_bases[1] = 0x00000000;
199 ram_sizes[1] = 0x00000000;
200 ram_size = 128 * 1024 * 1024;
201 #ifdef DEBUG_BOARD_INIT
202 printf("%s: register cpu\n", __func__);
204 env = ppc405ep_init(ram_bases, ram_sizes, 33333333, &pic, &sram_offset,
205 kernel_filename == NULL ? 0 : 1);
207 #ifdef DEBUG_BOARD_INIT
208 printf("%s: register SRAM at offset %08lx\n", __func__, sram_offset);
210 sram_size = 512 * 1024;
211 cpu_register_physical_memory(0xFFF00000, sram_size,
212 sram_offset | IO_MEM_RAM);
213 /* allocate and load BIOS */
214 #ifdef DEBUG_BOARD_INIT
215 printf("%s: register BIOS\n", __func__);
217 bios_offset = sram_offset + sram_size;
219 #ifdef USE_FLASH_BIOS
220 if (pflash_table[fl_idx] != NULL) {
221 bios_size = bdrv_getlength(pflash_table[fl_idx]);
222 fl_sectors = (bios_size + 65535) >> 16;
223 #ifdef DEBUG_BOARD_INIT
224 printf("Register parallel flash %d size " ADDRX " at offset %08lx "
225 " addr " ADDRX " '%s' %d\n",
226 fl_idx, bios_size, bios_offset, -bios_size,
227 bdrv_get_device_name(pflash_table[fl_idx]), fl_sectors);
229 pflash_register((uint32_t)(-bios_size), bios_offset,
230 pflash_table[fl_idx], 65536, fl_sectors, 2,
231 0x0001, 0x22DA, 0x0000, 0x0000);
236 #ifdef DEBUG_BOARD_INIT
237 printf("Load BIOS from file\n");
239 if (bios_name == NULL)
240 bios_name = BIOS_FILENAME;
241 snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
242 bios_size = load_image(buf, phys_ram_base + bios_offset);
243 if (bios_size < 0 || bios_size > BIOS_SIZE) {
244 fprintf(stderr, "qemu: could not load PowerPC bios '%s'\n", buf);
247 bios_size = (bios_size + 0xfff) & ~0xfff;
248 cpu_register_physical_memory((uint32_t)(-bios_size),
249 bios_size, bios_offset | IO_MEM_ROM);
251 bios_offset += bios_size;
253 #ifdef DEBUG_BOARD_INIT
254 printf("%s: register FPGA\n", __func__);
256 ref405ep_fpga_init(0xF0300000);
258 #ifdef DEBUG_BOARD_INIT
259 printf("%s: register NVRAM\n", __func__);
261 m48t59_init(NULL, 0xF0000000, 0, 8192, 8);
263 linux_boot = (kernel_filename != NULL);
265 #ifdef DEBUG_BOARD_INIT
266 printf("%s: load kernel\n", __func__);
268 memset(&bd, 0, sizeof(bd));
269 bd.bi_memstart = 0x00000000;
270 bd.bi_memsize = ram_size;
271 bd.bi_flashstart = -bios_size;
272 bd.bi_flashsize = -bios_size;
273 bd.bi_flashoffset = 0;
274 bd.bi_sramstart = 0xFFF00000;
275 bd.bi_sramsize = sram_size;
277 bd.bi_intfreq = 133333333;
278 bd.bi_busfreq = 33333333;
279 bd.bi_baudrate = 115200;
280 bd.bi_s_version[0] = 'Q';
281 bd.bi_s_version[1] = 'M';
282 bd.bi_s_version[2] = 'U';
283 bd.bi_s_version[3] = '\0';
284 bd.bi_r_version[0] = 'Q';
285 bd.bi_r_version[1] = 'E';
286 bd.bi_r_version[2] = 'M';
287 bd.bi_r_version[3] = 'U';
288 bd.bi_r_version[4] = '\0';
289 bd.bi_procfreq = 133333333;
290 bd.bi_plb_busfreq = 33333333;
291 bd.bi_pci_busfreq = 33333333;
292 bd.bi_opbfreq = 33333333;
293 bdloc = ppc405_set_bootinfo(env, &bd, 0x00000001);
295 kernel_base = KERNEL_LOAD_ADDR;
296 /* now we can load the kernel */
297 kernel_size = load_image(kernel_filename, phys_ram_base + kernel_base);
298 if (kernel_size < 0) {
299 fprintf(stderr, "qemu: could not load kernel '%s'\n",
303 printf("Load kernel size " TARGET_FMT_ld " at " TARGET_FMT_lx
304 " %02x %02x %02x %02x\n", kernel_size, kernel_base,
305 *(char *)(phys_ram_base + kernel_base),
306 *(char *)(phys_ram_base + kernel_base + 1),
307 *(char *)(phys_ram_base + kernel_base + 2),
308 *(char *)(phys_ram_base + kernel_base + 3));
310 if (initrd_filename) {
311 initrd_base = INITRD_LOAD_ADDR;
312 initrd_size = load_image(initrd_filename,
313 phys_ram_base + initrd_base);
314 if (initrd_size < 0) {
315 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
323 env->gpr[4] = initrd_base;
324 env->gpr[5] = initrd_size;
326 if (kernel_cmdline != NULL) {
327 len = strlen(kernel_cmdline);
328 bdloc -= ((len + 255) & ~255);
329 memcpy(phys_ram_base + bdloc, kernel_cmdline, len + 1);
331 env->gpr[7] = bdloc + len;
336 env->nip = KERNEL_LOAD_ADDR;
344 #ifdef DEBUG_BOARD_INIT
345 printf("%s: Done\n", __func__);
347 printf("bdloc %016lx %s\n",
348 (unsigned long)bdloc, (char *)(phys_ram_base + bdloc));
351 QEMUMachine ref405ep_machine = {
357 /*****************************************************************************/
358 /* AMCC Taihu evaluation board */
359 /* - PowerPC 405EP processor
360 * - SDRAM 128 MB at 0x00000000
361 * - Boot flash 2 MB at 0xFFE00000
362 * - Application flash 32 MB at 0xFC000000
365 * - 1 USB 1.1 device 0x50000000
366 * - 1 LCD display 0x50100000
367 * - 1 CPLD 0x50100000
369 * - 1 I2C thermal sensor
371 * - bit-bang SPI port using GPIOs
372 * - 1 EBC interface connector 0 0x50200000
373 * - 1 cardbus controller + expansion slot.
374 * - 1 PCI expansion slot.
376 typedef struct taihu_cpld_t taihu_cpld_t;
377 struct taihu_cpld_t {
383 static uint32_t taihu_cpld_readb (void *opaque, target_phys_addr_t addr)
405 static void taihu_cpld_writeb (void *opaque,
406 target_phys_addr_t addr, uint32_t value)
424 static uint32_t taihu_cpld_readw (void *opaque, target_phys_addr_t addr)
428 ret = taihu_cpld_readb(opaque, addr) << 8;
429 ret |= taihu_cpld_readb(opaque, addr + 1);
434 static void taihu_cpld_writew (void *opaque,
435 target_phys_addr_t addr, uint32_t value)
437 taihu_cpld_writeb(opaque, addr, (value >> 8) & 0xFF);
438 taihu_cpld_writeb(opaque, addr + 1, value & 0xFF);
441 static uint32_t taihu_cpld_readl (void *opaque, target_phys_addr_t addr)
445 ret = taihu_cpld_readb(opaque, addr) << 24;
446 ret |= taihu_cpld_readb(opaque, addr + 1) << 16;
447 ret |= taihu_cpld_readb(opaque, addr + 2) << 8;
448 ret |= taihu_cpld_readb(opaque, addr + 3);
453 static void taihu_cpld_writel (void *opaque,
454 target_phys_addr_t addr, uint32_t value)
456 taihu_cpld_writel(opaque, addr, (value >> 24) & 0xFF);
457 taihu_cpld_writel(opaque, addr + 1, (value >> 16) & 0xFF);
458 taihu_cpld_writel(opaque, addr + 2, (value >> 8) & 0xFF);
459 taihu_cpld_writeb(opaque, addr + 3, value & 0xFF);
462 static CPUReadMemoryFunc *taihu_cpld_read[] = {
468 static CPUWriteMemoryFunc *taihu_cpld_write[] = {
474 static void taihu_cpld_reset (void *opaque)
483 static void taihu_cpld_init (uint32_t base)
488 cpld = qemu_mallocz(sizeof(taihu_cpld_t));
491 cpld_memory = cpu_register_io_memory(0, taihu_cpld_read,
492 taihu_cpld_write, cpld);
493 cpu_register_physical_memory(base, 0x00000100, cpld_memory);
494 taihu_cpld_reset(cpld);
495 qemu_register_reset(&taihu_cpld_reset, cpld);
499 static void taihu_405ep_init(int ram_size, int vga_ram_size, int boot_device,
500 DisplayState *ds, const char **fd_filename,
502 const char *kernel_filename,
503 const char *kernel_cmdline,
504 const char *initrd_filename,
505 const char *cpu_model)
510 ram_addr_t bios_offset;
511 target_phys_addr_t ram_bases[2], ram_sizes[2];
512 target_ulong bios_size;
513 target_ulong kernel_base, kernel_size, initrd_base, initrd_size;
515 int fl_idx, fl_sectors;
517 /* RAM is soldered to the board so the size cannot be changed */
518 ram_bases[0] = 0x00000000;
519 ram_sizes[0] = 0x04000000;
520 ram_bases[1] = 0x04000000;
521 ram_sizes[1] = 0x04000000;
522 #ifdef DEBUG_BOARD_INIT
523 printf("%s: register cpu\n", __func__);
525 env = ppc405ep_init(ram_bases, ram_sizes, 33333333, &pic, &bios_offset,
526 kernel_filename == NULL ? 0 : 1);
527 /* allocate and load BIOS */
528 #ifdef DEBUG_BOARD_INIT
529 printf("%s: register BIOS\n", __func__);
532 #if defined(USE_FLASH_BIOS)
533 if (pflash_table[fl_idx] != NULL) {
534 bios_size = bdrv_getlength(pflash_table[fl_idx]);
535 /* XXX: should check that size is 2MB */
536 // bios_size = 2 * 1024 * 1024;
537 fl_sectors = (bios_size + 65535) >> 16;
538 #ifdef DEBUG_BOARD_INIT
539 printf("Register parallel flash %d size " ADDRX " at offset %08lx "
540 " addr " ADDRX " '%s' %d\n",
541 fl_idx, bios_size, bios_offset, -bios_size,
542 bdrv_get_device_name(pflash_table[fl_idx]), fl_sectors);
544 pflash_register((uint32_t)(-bios_size), bios_offset,
545 pflash_table[fl_idx], 65536, fl_sectors, 4,
546 0x0001, 0x22DA, 0x0000, 0x0000);
551 #ifdef DEBUG_BOARD_INIT
552 printf("Load BIOS from file\n");
554 if (bios_name == NULL)
555 bios_name = BIOS_FILENAME;
556 snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
557 bios_size = load_image(buf, phys_ram_base + bios_offset);
558 if (bios_size < 0 || bios_size > BIOS_SIZE) {
559 fprintf(stderr, "qemu: could not load PowerPC bios '%s'\n", buf);
562 bios_size = (bios_size + 0xfff) & ~0xfff;
563 cpu_register_physical_memory((uint32_t)(-bios_size),
564 bios_size, bios_offset | IO_MEM_ROM);
566 bios_offset += bios_size;
567 /* Register Linux flash */
568 if (pflash_table[fl_idx] != NULL) {
569 bios_size = bdrv_getlength(pflash_table[fl_idx]);
570 /* XXX: should check that size is 32MB */
571 bios_size = 32 * 1024 * 1024;
572 fl_sectors = (bios_size + 65535) >> 16;
573 #ifdef DEBUG_BOARD_INIT
574 printf("Register parallel flash %d size " ADDRX " at offset %08lx "
575 " addr " ADDRX " '%s'\n",
576 fl_idx, bios_size, bios_offset, (target_ulong)0xfc000000,
577 bdrv_get_device_name(pflash_table[fl_idx]));
579 pflash_register(0xfc000000, bios_offset, pflash_table[fl_idx],
580 65536, fl_sectors, 4,
581 0x0001, 0x22DA, 0x0000, 0x0000);
584 /* Register CLPD & LCD display */
585 #ifdef DEBUG_BOARD_INIT
586 printf("%s: register CPLD\n", __func__);
588 taihu_cpld_init(0x50100000);
590 linux_boot = (kernel_filename != NULL);
592 #ifdef DEBUG_BOARD_INIT
593 printf("%s: load kernel\n", __func__);
595 kernel_base = KERNEL_LOAD_ADDR;
596 /* now we can load the kernel */
597 kernel_size = load_image(kernel_filename, phys_ram_base + kernel_base);
598 if (kernel_size < 0) {
599 fprintf(stderr, "qemu: could not load kernel '%s'\n",
604 if (initrd_filename) {
605 initrd_base = INITRD_LOAD_ADDR;
606 initrd_size = load_image(initrd_filename,
607 phys_ram_base + initrd_base);
608 if (initrd_size < 0) {
610 "qemu: could not load initial ram disk '%s'\n",
625 #ifdef DEBUG_BOARD_INIT
626 printf("%s: Done\n", __func__);
630 QEMUMachine taihu_machine = {