2 * QEMU PowerPC 405 shared definitions
4 * Copyright (c) 2007 Jocelyn Mayer
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7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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25 #if !defined(PPC_405_H)
28 /* Bootinfo as set-up by u-boot */
29 typedef struct ppc4xx_bd_info_t ppc4xx_bd_info_t;
30 struct ppc4xx_bd_info_t {
33 uint32_t bi_flashstart;
34 uint32_t bi_flashsize;
35 uint32_t bi_flashoffset; /* 0x10 */
36 uint32_t bi_sramstart;
38 uint32_t bi_bootflags;
39 uint32_t bi_ipaddr; /* 0x20 */
40 uint8_t bi_enetaddr[6];
43 uint32_t bi_busfreq; /* 0x30 */
45 uint8_t bi_s_version[4];
46 uint8_t bi_r_version[32];
48 uint32_t bi_plb_busfreq;
49 uint32_t bi_pci_busfreq;
50 uint8_t bi_pci_enetaddr[6];
51 uint32_t bi_pci_enetaddr2[6];
53 uint32_t bi_iic_fast[2];
56 /* PowerPC 405 core */
57 CPUState *ppc405_init (const unsigned char *cpu_model,
58 clk_setup_t *cpu_clk, clk_setup_t *tb_clk,
60 ram_addr_t ppc405_set_bootinfo (CPUState *env, ppc4xx_bd_info_t *bd);
62 void ppc40x_core_reset (CPUState *env);
63 void ppc40x_chip_reset (CPUState *env);
64 void ppc40x_system_reset (CPUState *env);
66 typedef struct ppc4xx_mmio_t ppc4xx_mmio_t;
67 int ppc4xx_mmio_register (CPUState *env, ppc4xx_mmio_t *mmio,
68 uint32_t offset, uint32_t len,
69 CPUReadMemoryFunc **mem_read,
70 CPUWriteMemoryFunc **mem_write, void *opaque);
71 ppc4xx_mmio_t *ppc4xx_mmio_init (CPUState *env, uint32_t base);
72 /* PowerPC 4xx peripheral local bus arbitrer */
73 void ppc4xx_plb_init (CPUState *env);
74 /* PLB to OPB bridge */
75 void ppc4xx_pob_init (CPUState *env);
77 void ppc4xx_opba_init (CPUState *env, ppc4xx_mmio_t *mmio, uint32_t offset);
78 /* PowerPC 4xx universal interrupt controller */
80 PPCUIC_OUTPUT_INT = 0,
81 PPCUIC_OUTPUT_CINT = 1,
84 qemu_irq *ppcuic_init (CPUState *env, qemu_irq *irqs,
85 uint32_t dcr_base, int has_ssr, int has_vr);
86 /* SDRAM controller */
87 void ppc405_sdram_init (CPUState *env, qemu_irq irq, int nbanks,
88 target_ulong *ram_bases, target_ulong *ram_sizes,
90 /* Peripheral controller */
91 void ppc405_ebc_init (CPUState *env);
93 void ppc405_dma_init (CPUState *env, qemu_irq irqs[4]);
95 void ppc405_gpio_init (CPUState *env, ppc4xx_mmio_t *mmio, uint32_t offset);
97 void ppc405_serial_init (CPUState *env, ppc4xx_mmio_t *mmio,
98 uint32_t offset, qemu_irq irq,
99 CharDriverState *chr);
101 void ppc405_ocm_init (CPUState *env, unsigned long offset);
103 void ppc405_i2c_init (CPUState *env, ppc4xx_mmio_t *mmio, uint32_t offset);
104 /* PowerPC 405 microcontrollers */
105 CPUState *ppc405cr_init (target_ulong ram_bases[4], target_ulong ram_sizes[4],
106 uint32_t sysclk, qemu_irq **picp,
107 ram_addr_t *offsetp, int do_init);
108 CPUState *ppc405ep_init (target_ulong ram_bases[2], target_ulong ram_sizes[2],
109 uint32_t sysclk, qemu_irq **picp,
110 ram_addr_t *offsetp, int do_init);
111 /* IBM STBxxx microcontrollers */
112 CPUState *ppc_stb025_init (target_ulong ram_bases[2],
113 target_ulong ram_sizes[2],
114 uint32_t sysclk, qemu_irq **picp,
115 ram_addr_t *offsetp);
117 #endif /* !defined(PPC_405_H) */