2 * QEMU generic PPC hardware System Emulator
4 * Copyright (c) 2003-2007 Jocelyn Mayer
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
30 /*****************************************************************************/
31 /* PowerPC internal fake IRQ controller
32 * used to manage multiple sources hardware events
34 static void ppc_set_irq (void *opaque, int n_IRQ, int level)
40 env->pending_interrupts |= 1 << n_IRQ;
41 cpu_interrupt(env, CPU_INTERRUPT_HARD);
43 env->pending_interrupts &= ~(1 << n_IRQ);
44 if (env->pending_interrupts == 0)
45 cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
48 printf("%s: %p n_IRQ %d level %d => pending %08x req %08x\n", __func__,
49 env, n_IRQ, level, env->pending_interrupts, env->interrupt_request);
53 void cpu_ppc_irq_init_cpu(CPUState *env)
58 qi = qemu_allocate_irqs(ppc_set_irq, env, 32);
59 for (i = 0; i < 32; i++) {
64 /* External IRQ callback from OpenPIC IRQ controller */
65 void ppc_openpic_irq (void *opaque, int n_IRQ, int level)
69 n_IRQ = PPC_INTERRUPT_EXT;
71 case OPENPIC_EVT_CINT:
72 /* On PowerPC BookE, critical input use vector 0 */
73 n_IRQ = PPC_INTERRUPT_RESET;
76 n_IRQ = PPC_INTERRUPT_MCK;
78 case OPENPIC_EVT_DEBUG:
79 n_IRQ = PPC_INTERRUPT_DEBUG;
81 case OPENPIC_EVT_RESET:
82 qemu_system_reset_request();
85 ppc_set_irq(opaque, n_IRQ, level);
88 /*****************************************************************************/
89 /* PPC time base and decrementer emulation */
93 /* Time base management */
94 int64_t tb_offset; /* Compensation */
95 uint32_t tb_freq; /* TB frequency */
96 /* Decrementer management */
97 uint64_t decr_next; /* Tick for next decr interrupt */
98 struct QEMUTimer *decr_timer;
102 static inline uint64_t cpu_ppc_get_tb (ppc_tb_t *tb_env)
104 /* TB time in tb periods */
105 return muldiv64(qemu_get_clock(vm_clock) + tb_env->tb_offset,
106 tb_env->tb_freq, ticks_per_sec);
109 uint32_t cpu_ppc_load_tbl (CPUState *env)
111 ppc_tb_t *tb_env = env->tb_env;
114 tb = cpu_ppc_get_tb(tb_env);
117 static int last_time;
120 if (last_time != now) {
122 printf("%s: tb=0x%016lx %d %08lx\n",
123 __func__, tb, now, tb_env->tb_offset);
128 return tb & 0xFFFFFFFF;
131 uint32_t cpu_ppc_load_tbu (CPUState *env)
133 ppc_tb_t *tb_env = env->tb_env;
136 tb = cpu_ppc_get_tb(tb_env);
138 printf("%s: tb=0x%016lx\n", __func__, tb);
144 static void cpu_ppc_store_tb (ppc_tb_t *tb_env, uint64_t value)
146 tb_env->tb_offset = muldiv64(value, ticks_per_sec, tb_env->tb_freq)
147 - qemu_get_clock(vm_clock);
149 printf("%s: tb=0x%016lx offset=%08x\n", __func__, value);
153 void cpu_ppc_store_tbu (CPUState *env, uint32_t value)
155 ppc_tb_t *tb_env = env->tb_env;
157 cpu_ppc_store_tb(tb_env,
158 ((uint64_t)value << 32) | cpu_ppc_load_tbl(env));
161 void cpu_ppc_store_tbl (CPUState *env, uint32_t value)
163 ppc_tb_t *tb_env = env->tb_env;
165 cpu_ppc_store_tb(tb_env,
166 ((uint64_t)cpu_ppc_load_tbu(env) << 32) | value);
169 uint32_t cpu_ppc_load_decr (CPUState *env)
171 ppc_tb_t *tb_env = env->tb_env;
175 diff = tb_env->decr_next - qemu_get_clock(vm_clock);
177 decr = muldiv64(diff, tb_env->tb_freq, ticks_per_sec);
179 decr = -muldiv64(-diff, tb_env->tb_freq, ticks_per_sec);
180 #if defined(DEBUG_TB)
181 printf("%s: 0x%08x\n", __func__, decr);
187 /* When decrementer expires,
188 * all we need to do is generate or queue a CPU exception
190 static inline void cpu_ppc_decr_excp (CPUState *env)
194 printf("raise decrementer exception\n");
196 ppc_set_irq(env, PPC_INTERRUPT_DECR, 1);
199 static void _cpu_ppc_store_decr (CPUState *env, uint32_t decr,
200 uint32_t value, int is_excp)
202 ppc_tb_t *tb_env = env->tb_env;
206 printf("%s: 0x%08x => 0x%08x\n", __func__, decr, value);
208 now = qemu_get_clock(vm_clock);
209 next = now + muldiv64(value, ticks_per_sec, tb_env->tb_freq);
211 next += tb_env->decr_next - now;
214 tb_env->decr_next = next;
216 qemu_mod_timer(tb_env->decr_timer, next);
217 /* If we set a negative value and the decrementer was positive,
218 * raise an exception.
220 if ((value & 0x80000000) && !(decr & 0x80000000))
221 cpu_ppc_decr_excp(env);
224 void cpu_ppc_store_decr (CPUState *env, uint32_t value)
226 _cpu_ppc_store_decr(env, cpu_ppc_load_decr(env), value, 0);
229 static void cpu_ppc_decr_cb (void *opaque)
231 _cpu_ppc_store_decr(opaque, 0x00000000, 0xFFFFFFFF, 1);
234 /* Set up (once) timebase frequency (in Hz) */
235 ppc_tb_t *cpu_ppc_tb_init (CPUState *env, uint32_t freq)
239 tb_env = qemu_mallocz(sizeof(ppc_tb_t));
242 env->tb_env = tb_env;
243 if (tb_env->tb_freq == 0 || 1) {
244 tb_env->tb_freq = freq;
245 /* Create new timer */
247 qemu_new_timer(vm_clock, &cpu_ppc_decr_cb, env);
248 /* There is a bug in Linux 2.4 kernels:
249 * if a decrementer exception is pending when it enables msr_ee,
250 * it's not ready to handle it...
252 _cpu_ppc_store_decr(env, 0xFFFFFFFF, 0xFFFFFFFF, 0);
258 /* Specific helpers for POWER & PowerPC 601 RTC */
259 ppc_tb_t *cpu_ppc601_rtc_init (CPUState *env)
261 return cpu_ppc_tb_init(env, 7812500);
264 void cpu_ppc601_store_rtcu (CPUState *env, uint32_t value)
265 __attribute__ (( alias ("cpu_ppc_store_tbu") ));
267 uint32_t cpu_ppc601_load_rtcu (CPUState *env)
268 __attribute__ (( alias ("cpu_ppc_load_tbu") ));
270 void cpu_ppc601_store_rtcl (CPUState *env, uint32_t value)
272 cpu_ppc_store_tbl(env, value & 0x3FFFFF80);
275 uint32_t cpu_ppc601_load_rtcl (CPUState *env)
277 return cpu_ppc_load_tbl(env) & 0x3FFFFF80;
280 /*****************************************************************************/
281 /* Embedded PowerPC timers */
284 typedef struct ppcemb_timer_t ppcemb_timer_t;
285 struct ppcemb_timer_t {
286 uint64_t pit_reload; /* PIT auto-reload value */
287 uint64_t fit_next; /* Tick for next FIT interrupt */
288 struct QEMUTimer *fit_timer;
289 uint64_t wdt_next; /* Tick for next WDT interrupt */
290 struct QEMUTimer *wdt_timer;
293 /* Fixed interval timer */
294 static void cpu_4xx_fit_cb (void *opaque)
298 ppcemb_timer_t *ppcemb_timer;
302 tb_env = env->tb_env;
303 ppcemb_timer = tb_env->opaque;
304 now = qemu_get_clock(vm_clock);
305 switch ((env->spr[SPR_40x_TCR] >> 24) & 0x3) {
319 /* Cannot occur, but makes gcc happy */
322 next = now + muldiv64(next, ticks_per_sec, tb_env->tb_freq);
325 qemu_mod_timer(ppcemb_timer->fit_timer, next);
326 tb_env->decr_next = next;
327 env->spr[SPR_40x_TSR] |= 1 << 26;
328 if ((env->spr[SPR_40x_TCR] >> 23) & 0x1)
329 ppc_set_irq(env, PPC_INTERRUPT_FIT, 1);
331 fprintf(logfile, "%s: ir %d TCR %08x TSR %08x\n", __func__,
332 (env->spr[SPR_40x_TCR] >> 23) & 0x1,
333 env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]);
337 /* Programmable interval timer */
338 static void cpu_4xx_pit_cb (void *opaque)
342 ppcemb_timer_t *ppcemb_timer;
346 tb_env = env->tb_env;
347 ppcemb_timer = tb_env->opaque;
348 now = qemu_get_clock(vm_clock);
349 if ((env->spr[SPR_40x_TCR] >> 22) & 0x1) {
351 next = now + muldiv64(ppcemb_timer->pit_reload,
352 ticks_per_sec, tb_env->tb_freq);
355 qemu_mod_timer(tb_env->decr_timer, next);
356 tb_env->decr_next = next;
358 env->spr[SPR_40x_TSR] |= 1 << 27;
359 if ((env->spr[SPR_40x_TCR] >> 26) & 0x1)
360 ppc_set_irq(env, PPC_INTERRUPT_PIT, 1);
362 fprintf(logfile, "%s: ar %d ir %d TCR %08x TSR %08x %08lx\n", __func__,
363 (env->spr[SPR_40x_TCR] >> 22) & 0x1,
364 (env->spr[SPR_40x_TCR] >> 26) & 0x1,
365 env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR],
366 ppcemb_timer->pit_reload);
371 static void cpu_4xx_wdt_cb (void *opaque)
375 ppcemb_timer_t *ppcemb_timer;
379 tb_env = env->tb_env;
380 ppcemb_timer = tb_env->opaque;
381 now = qemu_get_clock(vm_clock);
382 switch ((env->spr[SPR_40x_TCR] >> 30) & 0x3) {
396 /* Cannot occur, but makes gcc happy */
399 next = now + muldiv64(next, ticks_per_sec, tb_env->tb_freq);
403 fprintf(logfile, "%s: TCR %08x TSR %08x\n", __func__,
404 env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]);
406 switch ((env->spr[SPR_40x_TSR] >> 30) & 0x3) {
409 qemu_mod_timer(ppcemb_timer->wdt_timer, next);
410 ppcemb_timer->wdt_next = next;
411 env->spr[SPR_40x_TSR] |= 1 << 31;
414 qemu_mod_timer(ppcemb_timer->wdt_timer, next);
415 ppcemb_timer->wdt_next = next;
416 env->spr[SPR_40x_TSR] |= 1 << 30;
417 if ((env->spr[SPR_40x_TCR] >> 27) & 0x1)
418 ppc_set_irq(env, PPC_INTERRUPT_WDT, 1);
421 env->spr[SPR_40x_TSR] &= ~0x30000000;
422 env->spr[SPR_40x_TSR] |= env->spr[SPR_40x_TCR] & 0x30000000;
423 switch ((env->spr[SPR_40x_TCR] >> 28) & 0x3) {
427 case 0x1: /* Core reset */
428 case 0x2: /* Chip reset */
429 case 0x3: /* System reset */
430 qemu_system_reset_request();
436 void store_40x_pit (CPUState *env, target_ulong val)
439 ppcemb_timer_t *ppcemb_timer;
442 tb_env = env->tb_env;
443 ppcemb_timer = tb_env->opaque;
445 fprintf(logfile, "%s %p %p\n", __func__, tb_env, ppcemb_timer);
446 ppcemb_timer->pit_reload = val;
450 fprintf(logfile, "%s: stop PIT\n", __func__);
451 qemu_del_timer(tb_env->decr_timer);
454 fprintf(logfile, "%s: start PIT 0x%08x\n", __func__, val);
455 now = qemu_get_clock(vm_clock);
456 next = now + muldiv64(val, ticks_per_sec, tb_env->tb_freq);
459 qemu_mod_timer(tb_env->decr_timer, next);
460 tb_env->decr_next = next;
464 target_ulong load_40x_pit (CPUState *env)
466 return cpu_ppc_load_decr(env);
469 void store_booke_tsr (CPUState *env, target_ulong val)
471 env->spr[SPR_40x_TSR] = val & 0xFC000000;
474 void store_booke_tcr (CPUState *env, target_ulong val)
476 /* We don't update timers now. Maybe we should... */
477 env->spr[SPR_40x_TCR] = val & 0xFF800000;
480 void ppc_emb_timers_init (CPUState *env)
483 ppcemb_timer_t *ppcemb_timer;
485 tb_env = env->tb_env;
486 ppcemb_timer = qemu_mallocz(sizeof(ppcemb_timer_t));
487 tb_env->opaque = ppcemb_timer;
489 fprintf(logfile, "%s %p %p\n", __func__, tb_env, ppcemb_timer);
490 if (ppcemb_timer != NULL) {
491 /* We use decr timer for PIT */
492 tb_env->decr_timer = qemu_new_timer(vm_clock, &cpu_4xx_pit_cb, env);
493 ppcemb_timer->fit_timer =
494 qemu_new_timer(vm_clock, &cpu_4xx_fit_cb, env);
495 ppcemb_timer->wdt_timer =
496 qemu_new_timer(vm_clock, &cpu_4xx_wdt_cb, env);
501 /*****************************************************************************/
502 /* Handle system reset (for now, just stop emulation) */
503 void cpu_ppc_reset (CPUState *env)
505 printf("Reset asked... Stop emulation\n");
510 /*****************************************************************************/
512 void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val)
524 printf("Set loglevel to %04x\n", val);
525 cpu_set_log(val | 0x100);
530 /*****************************************************************************/
532 void NVRAM_set_byte (m48t59_t *nvram, uint32_t addr, uint8_t value)
534 m48t59_write(nvram, addr, value);
537 uint8_t NVRAM_get_byte (m48t59_t *nvram, uint32_t addr)
539 return m48t59_read(nvram, addr);
542 void NVRAM_set_word (m48t59_t *nvram, uint32_t addr, uint16_t value)
544 m48t59_write(nvram, addr, value >> 8);
545 m48t59_write(nvram, addr + 1, value & 0xFF);
548 uint16_t NVRAM_get_word (m48t59_t *nvram, uint32_t addr)
552 tmp = m48t59_read(nvram, addr) << 8;
553 tmp |= m48t59_read(nvram, addr + 1);
557 void NVRAM_set_lword (m48t59_t *nvram, uint32_t addr, uint32_t value)
559 m48t59_write(nvram, addr, value >> 24);
560 m48t59_write(nvram, addr + 1, (value >> 16) & 0xFF);
561 m48t59_write(nvram, addr + 2, (value >> 8) & 0xFF);
562 m48t59_write(nvram, addr + 3, value & 0xFF);
565 uint32_t NVRAM_get_lword (m48t59_t *nvram, uint32_t addr)
569 tmp = m48t59_read(nvram, addr) << 24;
570 tmp |= m48t59_read(nvram, addr + 1) << 16;
571 tmp |= m48t59_read(nvram, addr + 2) << 8;
572 tmp |= m48t59_read(nvram, addr + 3);
577 void NVRAM_set_string (m48t59_t *nvram, uint32_t addr,
578 const unsigned char *str, uint32_t max)
582 for (i = 0; i < max && str[i] != '\0'; i++) {
583 m48t59_write(nvram, addr + i, str[i]);
585 m48t59_write(nvram, addr + max - 1, '\0');
588 int NVRAM_get_string (m48t59_t *nvram, uint8_t *dst, uint16_t addr, int max)
593 for (i = 0; i < max; i++) {
594 dst[i] = NVRAM_get_byte(nvram, addr + i);
602 static uint16_t NVRAM_crc_update (uint16_t prev, uint16_t value)
605 uint16_t pd, pd1, pd2;
610 pd2 = ((pd >> 4) & 0x000F) ^ pd1;
611 tmp ^= (pd1 << 3) | (pd1 << 8);
612 tmp ^= pd2 | (pd2 << 7) | (pd2 << 12);
617 uint16_t NVRAM_compute_crc (m48t59_t *nvram, uint32_t start, uint32_t count)
620 uint16_t crc = 0xFFFF;
625 for (i = 0; i != count; i++) {
626 crc = NVRAM_crc_update(crc, NVRAM_get_word(nvram, start + i));
629 crc = NVRAM_crc_update(crc, NVRAM_get_byte(nvram, start + i) << 8);
635 #define CMDLINE_ADDR 0x017ff000
637 int PPC_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size,
638 const unsigned char *arch,
639 uint32_t RAM_size, int boot_device,
640 uint32_t kernel_image, uint32_t kernel_size,
642 uint32_t initrd_image, uint32_t initrd_size,
643 uint32_t NVRAM_image,
644 int width, int height, int depth)
648 /* Set parameters for Open Hack'Ware BIOS */
649 NVRAM_set_string(nvram, 0x00, "QEMU_BIOS", 16);
650 NVRAM_set_lword(nvram, 0x10, 0x00000002); /* structure v2 */
651 NVRAM_set_word(nvram, 0x14, NVRAM_size);
652 NVRAM_set_string(nvram, 0x20, arch, 16);
653 NVRAM_set_lword(nvram, 0x30, RAM_size);
654 NVRAM_set_byte(nvram, 0x34, boot_device);
655 NVRAM_set_lword(nvram, 0x38, kernel_image);
656 NVRAM_set_lword(nvram, 0x3C, kernel_size);
658 /* XXX: put the cmdline in NVRAM too ? */
659 strcpy(phys_ram_base + CMDLINE_ADDR, cmdline);
660 NVRAM_set_lword(nvram, 0x40, CMDLINE_ADDR);
661 NVRAM_set_lword(nvram, 0x44, strlen(cmdline));
663 NVRAM_set_lword(nvram, 0x40, 0);
664 NVRAM_set_lword(nvram, 0x44, 0);
666 NVRAM_set_lword(nvram, 0x48, initrd_image);
667 NVRAM_set_lword(nvram, 0x4C, initrd_size);
668 NVRAM_set_lword(nvram, 0x50, NVRAM_image);
670 NVRAM_set_word(nvram, 0x54, width);
671 NVRAM_set_word(nvram, 0x56, height);
672 NVRAM_set_word(nvram, 0x58, depth);
673 crc = NVRAM_compute_crc(nvram, 0x00, 0xF8);
674 NVRAM_set_word(nvram, 0xFC, crc);