2 * QEMU generic PowerPC hardware System Emulator
4 * Copyright (c) 2003-2007 Jocelyn Mayer
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
27 //#define PPC_DEBUG_IRQ
28 //#define PPC_DEBUG_TB
33 void ppc_set_irq (CPUState *env, int n_IRQ, int level)
36 env->pending_interrupts |= 1 << n_IRQ;
37 cpu_interrupt(env, CPU_INTERRUPT_HARD);
39 env->pending_interrupts &= ~(1 << n_IRQ);
40 if (env->pending_interrupts == 0)
41 cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
43 #if defined(PPC_DEBUG_IRQ)
44 if (loglevel & CPU_LOG_INT) {
45 fprintf(logfile, "%s: %p n_IRQ %d level %d => pending %08x req %08x\n",
46 __func__, env, n_IRQ, level,
47 env->pending_interrupts, env->interrupt_request);
52 /* PowerPC 6xx / 7xx internal IRQ controller */
53 static void ppc6xx_set_irq (void *opaque, int pin, int level)
55 CPUState *env = opaque;
58 #if defined(PPC_DEBUG_IRQ)
59 if (loglevel & CPU_LOG_INT) {
60 fprintf(logfile, "%s: env %p pin %d level %d\n", __func__,
64 cur_level = (env->irq_input_state >> pin) & 1;
65 /* Don't generate spurious events */
66 if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) {
68 case PPC6xx_INPUT_INT:
69 /* Level sensitive - active high */
70 #if defined(PPC_DEBUG_IRQ)
71 if (loglevel & CPU_LOG_INT) {
72 fprintf(logfile, "%s: set the external IRQ state to %d\n",
76 ppc_set_irq(env, PPC_INTERRUPT_EXT, level);
78 case PPC6xx_INPUT_SMI:
79 /* Level sensitive - active high */
80 #if defined(PPC_DEBUG_IRQ)
81 if (loglevel & CPU_LOG_INT) {
82 fprintf(logfile, "%s: set the SMI IRQ state to %d\n",
86 ppc_set_irq(env, PPC_INTERRUPT_SMI, level);
88 case PPC6xx_INPUT_MCP:
89 /* Negative edge sensitive */
90 /* XXX: TODO: actual reaction may depends on HID0 status
91 * 603/604/740/750: check HID0[EMCP]
93 if (cur_level == 1 && level == 0) {
94 #if defined(PPC_DEBUG_IRQ)
95 if (loglevel & CPU_LOG_INT) {
96 fprintf(logfile, "%s: raise machine check state\n",
100 ppc_set_irq(env, PPC_INTERRUPT_MCK, 1);
103 case PPC6xx_INPUT_CKSTP_IN:
104 /* Level sensitive - active low */
105 /* XXX: TODO: relay the signal to CKSTP_OUT pin */
107 #if defined(PPC_DEBUG_IRQ)
108 if (loglevel & CPU_LOG_INT) {
109 fprintf(logfile, "%s: stop the CPU\n", __func__);
114 #if defined(PPC_DEBUG_IRQ)
115 if (loglevel & CPU_LOG_INT) {
116 fprintf(logfile, "%s: restart the CPU\n", __func__);
122 case PPC6xx_INPUT_HRESET:
123 /* Level sensitive - active low */
126 #if defined(PPC_DEBUG_IRQ)
127 if (loglevel & CPU_LOG_INT) {
128 fprintf(logfile, "%s: reset the CPU\n", __func__);
135 case PPC6xx_INPUT_SRESET:
136 #if defined(PPC_DEBUG_IRQ)
137 if (loglevel & CPU_LOG_INT) {
138 fprintf(logfile, "%s: set the RESET IRQ state to %d\n",
142 ppc_set_irq(env, PPC_INTERRUPT_RESET, level);
145 /* Unknown pin - do nothing */
146 #if defined(PPC_DEBUG_IRQ)
147 if (loglevel & CPU_LOG_INT) {
148 fprintf(logfile, "%s: unknown IRQ pin %d\n", __func__, pin);
154 env->irq_input_state |= 1 << pin;
156 env->irq_input_state &= ~(1 << pin);
160 void ppc6xx_irq_init (CPUState *env)
162 env->irq_inputs = (void **)qemu_allocate_irqs(&ppc6xx_set_irq, env, 6);
165 /* PowerPC 970 internal IRQ controller */
166 static void ppc970_set_irq (void *opaque, int pin, int level)
168 CPUState *env = opaque;
171 #if defined(PPC_DEBUG_IRQ)
172 if (loglevel & CPU_LOG_INT) {
173 fprintf(logfile, "%s: env %p pin %d level %d\n", __func__,
177 cur_level = (env->irq_input_state >> pin) & 1;
178 /* Don't generate spurious events */
179 if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) {
181 case PPC970_INPUT_INT:
182 /* Level sensitive - active high */
183 #if defined(PPC_DEBUG_IRQ)
184 if (loglevel & CPU_LOG_INT) {
185 fprintf(logfile, "%s: set the external IRQ state to %d\n",
189 ppc_set_irq(env, PPC_INTERRUPT_EXT, level);
191 case PPC970_INPUT_THINT:
192 /* Level sensitive - active high */
193 #if defined(PPC_DEBUG_IRQ)
194 if (loglevel & CPU_LOG_INT) {
195 fprintf(logfile, "%s: set the SMI IRQ state to %d\n", __func__,
199 ppc_set_irq(env, PPC_INTERRUPT_THERM, level);
201 case PPC970_INPUT_MCP:
202 /* Negative edge sensitive */
203 /* XXX: TODO: actual reaction may depends on HID0 status
204 * 603/604/740/750: check HID0[EMCP]
206 if (cur_level == 1 && level == 0) {
207 #if defined(PPC_DEBUG_IRQ)
208 if (loglevel & CPU_LOG_INT) {
209 fprintf(logfile, "%s: raise machine check state\n",
213 ppc_set_irq(env, PPC_INTERRUPT_MCK, 1);
216 case PPC970_INPUT_CKSTP:
217 /* Level sensitive - active low */
218 /* XXX: TODO: relay the signal to CKSTP_OUT pin */
220 #if defined(PPC_DEBUG_IRQ)
221 if (loglevel & CPU_LOG_INT) {
222 fprintf(logfile, "%s: stop the CPU\n", __func__);
227 #if defined(PPC_DEBUG_IRQ)
228 if (loglevel & CPU_LOG_INT) {
229 fprintf(logfile, "%s: restart the CPU\n", __func__);
235 case PPC970_INPUT_HRESET:
236 /* Level sensitive - active low */
239 #if defined(PPC_DEBUG_IRQ)
240 if (loglevel & CPU_LOG_INT) {
241 fprintf(logfile, "%s: reset the CPU\n", __func__);
248 case PPC970_INPUT_SRESET:
249 #if defined(PPC_DEBUG_IRQ)
250 if (loglevel & CPU_LOG_INT) {
251 fprintf(logfile, "%s: set the RESET IRQ state to %d\n",
255 ppc_set_irq(env, PPC_INTERRUPT_RESET, level);
257 case PPC970_INPUT_TBEN:
258 #if defined(PPC_DEBUG_IRQ)
259 if (loglevel & CPU_LOG_INT) {
260 fprintf(logfile, "%s: set the TBEN state to %d\n", __func__,
267 /* Unknown pin - do nothing */
268 #if defined(PPC_DEBUG_IRQ)
269 if (loglevel & CPU_LOG_INT) {
270 fprintf(logfile, "%s: unknown IRQ pin %d\n", __func__, pin);
276 env->irq_input_state |= 1 << pin;
278 env->irq_input_state &= ~(1 << pin);
282 void ppc970_irq_init (CPUState *env)
284 env->irq_inputs = (void **)qemu_allocate_irqs(&ppc970_set_irq, env, 7);
287 /* PowerPC 405 internal IRQ controller */
288 static void ppc405_set_irq (void *opaque, int pin, int level)
290 CPUState *env = opaque;
293 #if defined(PPC_DEBUG_IRQ)
294 if (loglevel & CPU_LOG_INT) {
295 fprintf(logfile, "%s: env %p pin %d level %d\n", __func__,
299 cur_level = (env->irq_input_state >> pin) & 1;
300 /* Don't generate spurious events */
301 if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) {
303 case PPC405_INPUT_RESET_SYS:
305 #if defined(PPC_DEBUG_IRQ)
306 if (loglevel & CPU_LOG_INT) {
307 fprintf(logfile, "%s: reset the PowerPC system\n",
311 ppc40x_system_reset(env);
314 case PPC405_INPUT_RESET_CHIP:
316 #if defined(PPC_DEBUG_IRQ)
317 if (loglevel & CPU_LOG_INT) {
318 fprintf(logfile, "%s: reset the PowerPC chip\n", __func__);
321 ppc40x_chip_reset(env);
325 case PPC405_INPUT_RESET_CORE:
326 /* XXX: TODO: update DBSR[MRR] */
328 #if defined(PPC_DEBUG_IRQ)
329 if (loglevel & CPU_LOG_INT) {
330 fprintf(logfile, "%s: reset the PowerPC core\n", __func__);
333 ppc40x_core_reset(env);
336 case PPC405_INPUT_CINT:
337 /* Level sensitive - active high */
338 #if defined(PPC_DEBUG_IRQ)
339 if (loglevel & CPU_LOG_INT) {
340 fprintf(logfile, "%s: set the critical IRQ state to %d\n",
345 ppc_set_irq(env, PPC_INTERRUPT_RESET, level);
347 case PPC405_INPUT_INT:
348 /* Level sensitive - active high */
349 #if defined(PPC_DEBUG_IRQ)
350 if (loglevel & CPU_LOG_INT) {
351 fprintf(logfile, "%s: set the external IRQ state to %d\n",
355 ppc_set_irq(env, PPC_INTERRUPT_EXT, level);
357 case PPC405_INPUT_HALT:
358 /* Level sensitive - active low */
360 #if defined(PPC_DEBUG_IRQ)
361 if (loglevel & CPU_LOG_INT) {
362 fprintf(logfile, "%s: stop the CPU\n", __func__);
367 #if defined(PPC_DEBUG_IRQ)
368 if (loglevel & CPU_LOG_INT) {
369 fprintf(logfile, "%s: restart the CPU\n", __func__);
375 case PPC405_INPUT_DEBUG:
376 /* Level sensitive - active high */
377 #if defined(PPC_DEBUG_IRQ)
378 if (loglevel & CPU_LOG_INT) {
379 fprintf(logfile, "%s: set the debug pin state to %d\n",
383 ppc_set_irq(env, PPC_INTERRUPT_DEBUG, level);
386 /* Unknown pin - do nothing */
387 #if defined(PPC_DEBUG_IRQ)
388 if (loglevel & CPU_LOG_INT) {
389 fprintf(logfile, "%s: unknown IRQ pin %d\n", __func__, pin);
395 env->irq_input_state |= 1 << pin;
397 env->irq_input_state &= ~(1 << pin);
401 void ppc405_irq_init (CPUState *env)
403 env->irq_inputs = (void **)qemu_allocate_irqs(&ppc405_set_irq, env, 7);
406 /*****************************************************************************/
407 /* PowerPC time base and decrementer emulation */
409 /* Time base management */
410 int64_t tb_offset; /* Compensation */
411 int64_t atb_offset; /* Compensation */
412 uint32_t tb_freq; /* TB frequency */
413 /* Decrementer management */
414 uint64_t decr_next; /* Tick for next decr interrupt */
415 struct QEMUTimer *decr_timer;
416 #if defined(TARGET_PPC64H)
417 /* Hypervisor decrementer management */
418 uint64_t hdecr_next; /* Tick for next hdecr interrupt */
419 struct QEMUTimer *hdecr_timer;
426 static inline uint64_t cpu_ppc_get_tb (ppc_tb_t *tb_env, int64_t tb_offset)
428 /* TB time in tb periods */
429 return muldiv64(qemu_get_clock(vm_clock) + tb_env->tb_offset,
430 tb_env->tb_freq, ticks_per_sec);
433 uint32_t cpu_ppc_load_tbl (CPUState *env)
435 ppc_tb_t *tb_env = env->tb_env;
438 tb = cpu_ppc_get_tb(tb_env, tb_env->tb_offset);
439 #if defined(PPC_DEBUG_TB)
441 fprintf(logfile, "%s: tb=0x%016lx\n", __func__, tb);
445 return tb & 0xFFFFFFFF;
448 static inline uint32_t _cpu_ppc_load_tbu (CPUState *env)
450 ppc_tb_t *tb_env = env->tb_env;
453 tb = cpu_ppc_get_tb(tb_env, tb_env->tb_offset);
454 #if defined(PPC_DEBUG_TB)
456 fprintf(logfile, "%s: tb=0x%016lx\n", __func__, tb);
463 uint32_t cpu_ppc_load_tbu (CPUState *env)
465 return _cpu_ppc_load_tbu(env);
468 static inline void cpu_ppc_store_tb (ppc_tb_t *tb_env, int64_t *tb_offsetp,
471 *tb_offsetp = muldiv64(value, ticks_per_sec, tb_env->tb_freq)
472 - qemu_get_clock(vm_clock);
475 fprintf(logfile, "%s: tb=0x%016lx offset=%08lx\n", __func__, value,
481 void cpu_ppc_store_tbl (CPUState *env, uint32_t value)
483 ppc_tb_t *tb_env = env->tb_env;
486 tb = cpu_ppc_get_tb(tb_env, tb_env->tb_offset);
487 tb &= 0xFFFFFFFF00000000ULL;
488 cpu_ppc_store_tb(tb_env, &tb_env->tb_offset, tb | (uint64_t)value);
491 static inline void _cpu_ppc_store_tbu (CPUState *env, uint32_t value)
493 ppc_tb_t *tb_env = env->tb_env;
496 tb = cpu_ppc_get_tb(tb_env, tb_env->tb_offset);
497 tb &= 0x00000000FFFFFFFFULL;
498 cpu_ppc_store_tb(tb_env, &tb_env->tb_offset,
499 ((uint64_t)value << 32) | tb);
502 void cpu_ppc_store_tbu (CPUState *env, uint32_t value)
504 _cpu_ppc_store_tbu(env, value);
507 uint32_t cpu_ppc_load_atbl (CPUState *env)
509 ppc_tb_t *tb_env = env->tb_env;
512 tb = cpu_ppc_get_tb(tb_env, tb_env->atb_offset);
513 #if defined(PPC_DEBUG_TB)
515 fprintf(logfile, "%s: tb=0x%016lx\n", __func__, tb);
519 return tb & 0xFFFFFFFF;
522 uint32_t cpu_ppc_load_atbu (CPUState *env)
524 ppc_tb_t *tb_env = env->tb_env;
527 tb = cpu_ppc_get_tb(tb_env, tb_env->atb_offset);
528 #if defined(PPC_DEBUG_TB)
530 fprintf(logfile, "%s: tb=0x%016lx\n", __func__, tb);
537 void cpu_ppc_store_atbl (CPUState *env, uint32_t value)
539 ppc_tb_t *tb_env = env->tb_env;
542 tb = cpu_ppc_get_tb(tb_env, tb_env->atb_offset);
543 tb &= 0xFFFFFFFF00000000ULL;
544 cpu_ppc_store_tb(tb_env, &tb_env->atb_offset, tb | (uint64_t)value);
547 void cpu_ppc_store_atbu (CPUState *env, uint32_t value)
549 ppc_tb_t *tb_env = env->tb_env;
552 tb = cpu_ppc_get_tb(tb_env, tb_env->atb_offset);
553 tb &= 0x00000000FFFFFFFFULL;
554 cpu_ppc_store_tb(tb_env, &tb_env->atb_offset,
555 ((uint64_t)value << 32) | tb);
558 static inline uint32_t _cpu_ppc_load_decr (CPUState *env, uint64_t *next)
560 ppc_tb_t *tb_env = env->tb_env;
564 diff = tb_env->decr_next - qemu_get_clock(vm_clock);
566 decr = muldiv64(diff, tb_env->tb_freq, ticks_per_sec);
568 decr = -muldiv64(-diff, tb_env->tb_freq, ticks_per_sec);
569 #if defined(PPC_DEBUG_TB)
571 fprintf(logfile, "%s: 0x%08x\n", __func__, decr);
578 uint32_t cpu_ppc_load_decr (CPUState *env)
580 ppc_tb_t *tb_env = env->tb_env;
582 return _cpu_ppc_load_decr(env, &tb_env->decr_next);
585 #if defined(TARGET_PPC64H)
586 uint32_t cpu_ppc_load_hdecr (CPUState *env)
588 ppc_tb_t *tb_env = env->tb_env;
590 return _cpu_ppc_load_decr(env, &tb_env->hdecr_next);
593 uint64_t cpu_ppc_load_purr (CPUState *env)
595 ppc_tb_t *tb_env = env->tb_env;
598 diff = qemu_get_clock(vm_clock) - tb_env->purr_start;
600 return tb_env->purr_load + muldiv64(diff, tb_env->tb_freq, ticks_per_sec);
602 #endif /* defined(TARGET_PPC64H) */
604 /* When decrementer expires,
605 * all we need to do is generate or queue a CPU exception
607 static inline void cpu_ppc_decr_excp (CPUState *env)
612 fprintf(logfile, "raise decrementer exception\n");
615 ppc_set_irq(env, PPC_INTERRUPT_DECR, 1);
618 static inline void cpu_ppc_hdecr_excp (CPUState *env)
623 fprintf(logfile, "raise decrementer exception\n");
626 ppc_set_irq(env, PPC_INTERRUPT_HDECR, 1);
629 static void __cpu_ppc_store_decr (CPUState *env, uint64_t *nextp,
630 struct QEMUTimer *timer,
631 void (*raise_excp)(CPUState *),
632 uint32_t decr, uint32_t value,
635 ppc_tb_t *tb_env = env->tb_env;
640 fprintf(logfile, "%s: 0x%08x => 0x%08x\n", __func__, decr, value);
643 now = qemu_get_clock(vm_clock);
644 next = now + muldiv64(value, ticks_per_sec, tb_env->tb_freq);
646 next += *nextp - now;
651 qemu_mod_timer(timer, next);
652 /* If we set a negative value and the decrementer was positive,
653 * raise an exception.
655 if ((value & 0x80000000) && !(decr & 0x80000000))
660 static inline void _cpu_ppc_store_decr (CPUState *env, uint32_t decr,
661 uint32_t value, int is_excp)
663 ppc_tb_t *tb_env = env->tb_env;
665 __cpu_ppc_store_decr(env, &tb_env->decr_next, tb_env->decr_timer,
666 &cpu_ppc_decr_excp, decr, value, is_excp);
669 void cpu_ppc_store_decr (CPUState *env, uint32_t value)
671 _cpu_ppc_store_decr(env, cpu_ppc_load_decr(env), value, 0);
674 static void cpu_ppc_decr_cb (void *opaque)
676 _cpu_ppc_store_decr(opaque, 0x00000000, 0xFFFFFFFF, 1);
679 #if defined(TARGET_PPC64H)
680 static inline void _cpu_ppc_store_hdecr (CPUState *env, uint32_t hdecr,
681 uint32_t value, int is_excp)
683 ppc_tb_t *tb_env = env->tb_env;
685 __cpu_ppc_store_decr(env, &tb_env->hdecr_next, tb_env->hdecr_timer,
686 &cpu_ppc_hdecr_excp, hdecr, value, is_excp);
689 void cpu_ppc_store_hdecr (CPUState *env, uint32_t value)
691 _cpu_ppc_store_hdecr(env, cpu_ppc_load_hdecr(env), value, 0);
694 static void cpu_ppc_hdecr_cb (void *opaque)
696 _cpu_ppc_store_hdecr(opaque, 0x00000000, 0xFFFFFFFF, 1);
699 void cpu_ppc_store_purr (CPUState *env, uint64_t value)
701 ppc_tb_t *tb_env = env->tb_env;
703 tb_env->purr_load = value;
704 tb_env->purr_start = qemu_get_clock(vm_clock);
706 #endif /* defined(TARGET_PPC64H) */
708 static void cpu_ppc_set_tb_clk (void *opaque, uint32_t freq)
710 CPUState *env = opaque;
711 ppc_tb_t *tb_env = env->tb_env;
713 tb_env->tb_freq = freq;
714 /* There is a bug in Linux 2.4 kernels:
715 * if a decrementer exception is pending when it enables msr_ee at startup,
716 * it's not ready to handle it...
718 _cpu_ppc_store_decr(env, 0xFFFFFFFF, 0xFFFFFFFF, 0);
719 #if defined(TARGET_PPC64H)
720 _cpu_ppc_store_hdecr(env, 0xFFFFFFFF, 0xFFFFFFFF, 0);
721 cpu_ppc_store_purr(env, 0x0000000000000000ULL);
722 #endif /* defined(TARGET_PPC64H) */
725 /* Set up (once) timebase frequency (in Hz) */
726 clk_setup_cb cpu_ppc_tb_init (CPUState *env, uint32_t freq)
730 tb_env = qemu_mallocz(sizeof(ppc_tb_t));
733 env->tb_env = tb_env;
734 /* Create new timer */
735 tb_env->decr_timer = qemu_new_timer(vm_clock, &cpu_ppc_decr_cb, env);
736 #if defined(TARGET_PPC64H)
737 tb_env->hdecr_timer = qemu_new_timer(vm_clock, &cpu_ppc_hdecr_cb, env);
738 #endif /* defined(TARGET_PPC64H) */
739 cpu_ppc_set_tb_clk(env, freq);
741 return &cpu_ppc_set_tb_clk;
744 /* Specific helpers for POWER & PowerPC 601 RTC */
745 clk_setup_cb cpu_ppc601_rtc_init (CPUState *env)
747 return cpu_ppc_tb_init(env, 7812500);
750 void cpu_ppc601_store_rtcu (CPUState *env, uint32_t value)
752 _cpu_ppc_store_tbu(env, value);
755 uint32_t cpu_ppc601_load_rtcu (CPUState *env)
757 return _cpu_ppc_load_tbu(env);
760 void cpu_ppc601_store_rtcl (CPUState *env, uint32_t value)
762 cpu_ppc_store_tbl(env, value & 0x3FFFFF80);
765 uint32_t cpu_ppc601_load_rtcl (CPUState *env)
767 return cpu_ppc_load_tbl(env) & 0x3FFFFF80;
770 /*****************************************************************************/
771 /* Embedded PowerPC timers */
774 typedef struct ppcemb_timer_t ppcemb_timer_t;
775 struct ppcemb_timer_t {
776 uint64_t pit_reload; /* PIT auto-reload value */
777 uint64_t fit_next; /* Tick for next FIT interrupt */
778 struct QEMUTimer *fit_timer;
779 uint64_t wdt_next; /* Tick for next WDT interrupt */
780 struct QEMUTimer *wdt_timer;
783 /* Fixed interval timer */
784 static void cpu_4xx_fit_cb (void *opaque)
788 ppcemb_timer_t *ppcemb_timer;
792 tb_env = env->tb_env;
793 ppcemb_timer = tb_env->opaque;
794 now = qemu_get_clock(vm_clock);
795 switch ((env->spr[SPR_40x_TCR] >> 24) & 0x3) {
809 /* Cannot occur, but makes gcc happy */
812 next = now + muldiv64(next, ticks_per_sec, tb_env->tb_freq);
815 qemu_mod_timer(ppcemb_timer->fit_timer, next);
816 env->spr[SPR_40x_TSR] |= 1 << 26;
817 if ((env->spr[SPR_40x_TCR] >> 23) & 0x1)
818 ppc_set_irq(env, PPC_INTERRUPT_FIT, 1);
821 fprintf(logfile, "%s: ir %d TCR " ADDRX " TSR " ADDRX "\n", __func__,
822 (int)((env->spr[SPR_40x_TCR] >> 23) & 0x1),
823 env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]);
828 /* Programmable interval timer */
829 static void start_stop_pit (CPUState *env, ppc_tb_t *tb_env, int is_excp)
831 ppcemb_timer_t *ppcemb_timer;
834 ppcemb_timer = tb_env->opaque;
835 if (ppcemb_timer->pit_reload <= 1 ||
836 !((env->spr[SPR_40x_TCR] >> 26) & 0x1) ||
837 (is_excp && !((env->spr[SPR_40x_TCR] >> 22) & 0x1))) {
841 fprintf(logfile, "%s: stop PIT\n", __func__);
844 qemu_del_timer(tb_env->decr_timer);
848 fprintf(logfile, "%s: start PIT 0x" REGX "\n",
849 __func__, ppcemb_timer->pit_reload);
852 now = qemu_get_clock(vm_clock);
853 next = now + muldiv64(ppcemb_timer->pit_reload,
854 ticks_per_sec, tb_env->tb_freq);
856 next += tb_env->decr_next - now;
859 qemu_mod_timer(tb_env->decr_timer, next);
860 tb_env->decr_next = next;
864 static void cpu_4xx_pit_cb (void *opaque)
868 ppcemb_timer_t *ppcemb_timer;
871 tb_env = env->tb_env;
872 ppcemb_timer = tb_env->opaque;
873 env->spr[SPR_40x_TSR] |= 1 << 27;
874 if ((env->spr[SPR_40x_TCR] >> 26) & 0x1)
875 ppc_set_irq(env, PPC_INTERRUPT_PIT, 1);
876 start_stop_pit(env, tb_env, 1);
879 fprintf(logfile, "%s: ar %d ir %d TCR " ADDRX " TSR " ADDRX " "
880 "%016" PRIx64 "\n", __func__,
881 (int)((env->spr[SPR_40x_TCR] >> 22) & 0x1),
882 (int)((env->spr[SPR_40x_TCR] >> 26) & 0x1),
883 env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR],
884 ppcemb_timer->pit_reload);
890 static void cpu_4xx_wdt_cb (void *opaque)
894 ppcemb_timer_t *ppcemb_timer;
898 tb_env = env->tb_env;
899 ppcemb_timer = tb_env->opaque;
900 now = qemu_get_clock(vm_clock);
901 switch ((env->spr[SPR_40x_TCR] >> 30) & 0x3) {
915 /* Cannot occur, but makes gcc happy */
918 next = now + muldiv64(next, ticks_per_sec, tb_env->tb_freq);
923 fprintf(logfile, "%s: TCR " ADDRX " TSR " ADDRX "\n", __func__,
924 env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]);
927 switch ((env->spr[SPR_40x_TSR] >> 30) & 0x3) {
930 qemu_mod_timer(ppcemb_timer->wdt_timer, next);
931 ppcemb_timer->wdt_next = next;
932 env->spr[SPR_40x_TSR] |= 1 << 31;
935 qemu_mod_timer(ppcemb_timer->wdt_timer, next);
936 ppcemb_timer->wdt_next = next;
937 env->spr[SPR_40x_TSR] |= 1 << 30;
938 if ((env->spr[SPR_40x_TCR] >> 27) & 0x1)
939 ppc_set_irq(env, PPC_INTERRUPT_WDT, 1);
942 env->spr[SPR_40x_TSR] &= ~0x30000000;
943 env->spr[SPR_40x_TSR] |= env->spr[SPR_40x_TCR] & 0x30000000;
944 switch ((env->spr[SPR_40x_TCR] >> 28) & 0x3) {
948 case 0x1: /* Core reset */
949 ppc40x_core_reset(env);
951 case 0x2: /* Chip reset */
952 ppc40x_chip_reset(env);
954 case 0x3: /* System reset */
955 ppc40x_system_reset(env);
961 void store_40x_pit (CPUState *env, target_ulong val)
964 ppcemb_timer_t *ppcemb_timer;
966 tb_env = env->tb_env;
967 ppcemb_timer = tb_env->opaque;
970 fprintf(logfile, "%s %p %p\n", __func__, tb_env, ppcemb_timer);
973 ppcemb_timer->pit_reload = val;
974 start_stop_pit(env, tb_env, 0);
977 target_ulong load_40x_pit (CPUState *env)
979 return cpu_ppc_load_decr(env);
982 void store_booke_tsr (CPUState *env, target_ulong val)
986 fprintf(logfile, "%s: val=" ADDRX "\n", __func__, val);
989 env->spr[SPR_40x_TSR] &= ~(val & 0xFC000000);
990 if (val & 0x80000000)
991 ppc_set_irq(env, PPC_INTERRUPT_PIT, 0);
994 void store_booke_tcr (CPUState *env, target_ulong val)
998 tb_env = env->tb_env;
1000 if (loglevel != 0) {
1001 fprintf(logfile, "%s: val=" ADDRX "\n", __func__, val);
1004 env->spr[SPR_40x_TCR] = val & 0xFFC00000;
1005 start_stop_pit(env, tb_env, 1);
1006 cpu_4xx_wdt_cb(env);
1009 static void ppc_emb_set_tb_clk (void *opaque, uint32_t freq)
1011 CPUState *env = opaque;
1012 ppc_tb_t *tb_env = env->tb_env;
1015 if (loglevel != 0) {
1016 fprintf(logfile, "%s set new frequency to %u\n", __func__, freq);
1019 tb_env->tb_freq = freq;
1020 /* XXX: we should also update all timers */
1023 clk_setup_cb ppc_emb_timers_init (CPUState *env, uint32_t freq)
1026 ppcemb_timer_t *ppcemb_timer;
1028 tb_env = qemu_mallocz(sizeof(ppc_tb_t));
1029 if (tb_env == NULL) {
1032 env->tb_env = tb_env;
1033 ppcemb_timer = qemu_mallocz(sizeof(ppcemb_timer_t));
1034 tb_env->tb_freq = freq;
1035 tb_env->opaque = ppcemb_timer;
1037 if (loglevel != 0) {
1038 fprintf(logfile, "%s %p %p %p\n", __func__, tb_env, ppcemb_timer,
1039 &ppc_emb_set_tb_clk);
1042 if (ppcemb_timer != NULL) {
1043 /* We use decr timer for PIT */
1044 tb_env->decr_timer = qemu_new_timer(vm_clock, &cpu_4xx_pit_cb, env);
1045 ppcemb_timer->fit_timer =
1046 qemu_new_timer(vm_clock, &cpu_4xx_fit_cb, env);
1047 ppcemb_timer->wdt_timer =
1048 qemu_new_timer(vm_clock, &cpu_4xx_wdt_cb, env);
1051 return &ppc_emb_set_tb_clk;
1054 /*****************************************************************************/
1055 /* Embedded PowerPC Device Control Registers */
1056 typedef struct ppc_dcrn_t ppc_dcrn_t;
1058 dcr_read_cb dcr_read;
1059 dcr_write_cb dcr_write;
1063 /* XXX: on 460, DCR addresses are 32 bits wide,
1064 * using DCRIPR to get the 22 upper bits of the DCR address
1066 #define DCRN_NB 1024
1068 ppc_dcrn_t dcrn[DCRN_NB];
1069 int (*read_error)(int dcrn);
1070 int (*write_error)(int dcrn);
1073 int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, target_ulong *valp)
1077 if (dcrn < 0 || dcrn >= DCRN_NB)
1079 dcr = &dcr_env->dcrn[dcrn];
1080 if (dcr->dcr_read == NULL)
1082 *valp = (*dcr->dcr_read)(dcr->opaque, dcrn);
1087 if (dcr_env->read_error != NULL)
1088 return (*dcr_env->read_error)(dcrn);
1093 int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val)
1097 if (dcrn < 0 || dcrn >= DCRN_NB)
1099 dcr = &dcr_env->dcrn[dcrn];
1100 if (dcr->dcr_write == NULL)
1102 (*dcr->dcr_write)(dcr->opaque, dcrn, val);
1107 if (dcr_env->write_error != NULL)
1108 return (*dcr_env->write_error)(dcrn);
1113 int ppc_dcr_register (CPUState *env, int dcrn, void *opaque,
1114 dcr_read_cb dcr_read, dcr_write_cb dcr_write)
1119 dcr_env = env->dcr_env;
1120 if (dcr_env == NULL)
1122 if (dcrn < 0 || dcrn >= DCRN_NB)
1124 dcr = &dcr_env->dcrn[dcrn];
1125 if (dcr->opaque != NULL ||
1126 dcr->dcr_read != NULL ||
1127 dcr->dcr_write != NULL)
1129 dcr->opaque = opaque;
1130 dcr->dcr_read = dcr_read;
1131 dcr->dcr_write = dcr_write;
1136 int ppc_dcr_init (CPUState *env, int (*read_error)(int dcrn),
1137 int (*write_error)(int dcrn))
1141 dcr_env = qemu_mallocz(sizeof(ppc_dcr_t));
1142 if (dcr_env == NULL)
1144 dcr_env->read_error = read_error;
1145 dcr_env->write_error = write_error;
1146 env->dcr_env = dcr_env;
1153 /*****************************************************************************/
1154 /* Handle system reset (for now, just stop emulation) */
1155 void cpu_ppc_reset (CPUState *env)
1157 printf("Reset asked... Stop emulation\n");
1162 /*****************************************************************************/
1164 void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val)
1176 printf("Set loglevel to %04x\n", val);
1177 cpu_set_log(val | 0x100);
1182 /*****************************************************************************/
1184 void NVRAM_set_byte (m48t59_t *nvram, uint32_t addr, uint8_t value)
1186 m48t59_write(nvram, addr, value);
1189 uint8_t NVRAM_get_byte (m48t59_t *nvram, uint32_t addr)
1191 return m48t59_read(nvram, addr);
1194 void NVRAM_set_word (m48t59_t *nvram, uint32_t addr, uint16_t value)
1196 m48t59_write(nvram, addr, value >> 8);
1197 m48t59_write(nvram, addr + 1, value & 0xFF);
1200 uint16_t NVRAM_get_word (m48t59_t *nvram, uint32_t addr)
1204 tmp = m48t59_read(nvram, addr) << 8;
1205 tmp |= m48t59_read(nvram, addr + 1);
1209 void NVRAM_set_lword (m48t59_t *nvram, uint32_t addr, uint32_t value)
1211 m48t59_write(nvram, addr, value >> 24);
1212 m48t59_write(nvram, addr + 1, (value >> 16) & 0xFF);
1213 m48t59_write(nvram, addr + 2, (value >> 8) & 0xFF);
1214 m48t59_write(nvram, addr + 3, value & 0xFF);
1217 uint32_t NVRAM_get_lword (m48t59_t *nvram, uint32_t addr)
1221 tmp = m48t59_read(nvram, addr) << 24;
1222 tmp |= m48t59_read(nvram, addr + 1) << 16;
1223 tmp |= m48t59_read(nvram, addr + 2) << 8;
1224 tmp |= m48t59_read(nvram, addr + 3);
1229 void NVRAM_set_string (m48t59_t *nvram, uint32_t addr,
1230 const unsigned char *str, uint32_t max)
1234 for (i = 0; i < max && str[i] != '\0'; i++) {
1235 m48t59_write(nvram, addr + i, str[i]);
1237 m48t59_write(nvram, addr + max - 1, '\0');
1240 int NVRAM_get_string (m48t59_t *nvram, uint8_t *dst, uint16_t addr, int max)
1244 memset(dst, 0, max);
1245 for (i = 0; i < max; i++) {
1246 dst[i] = NVRAM_get_byte(nvram, addr + i);
1254 static uint16_t NVRAM_crc_update (uint16_t prev, uint16_t value)
1257 uint16_t pd, pd1, pd2;
1262 pd2 = ((pd >> 4) & 0x000F) ^ pd1;
1263 tmp ^= (pd1 << 3) | (pd1 << 8);
1264 tmp ^= pd2 | (pd2 << 7) | (pd2 << 12);
1269 uint16_t NVRAM_compute_crc (m48t59_t *nvram, uint32_t start, uint32_t count)
1272 uint16_t crc = 0xFFFF;
1277 for (i = 0; i != count; i++) {
1278 crc = NVRAM_crc_update(crc, NVRAM_get_word(nvram, start + i));
1281 crc = NVRAM_crc_update(crc, NVRAM_get_byte(nvram, start + i) << 8);
1287 #define CMDLINE_ADDR 0x017ff000
1289 int PPC_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size,
1290 const unsigned char *arch,
1291 uint32_t RAM_size, int boot_device,
1292 uint32_t kernel_image, uint32_t kernel_size,
1293 const char *cmdline,
1294 uint32_t initrd_image, uint32_t initrd_size,
1295 uint32_t NVRAM_image,
1296 int width, int height, int depth)
1300 /* Set parameters for Open Hack'Ware BIOS */
1301 NVRAM_set_string(nvram, 0x00, "QEMU_BIOS", 16);
1302 NVRAM_set_lword(nvram, 0x10, 0x00000002); /* structure v2 */
1303 NVRAM_set_word(nvram, 0x14, NVRAM_size);
1304 NVRAM_set_string(nvram, 0x20, arch, 16);
1305 NVRAM_set_lword(nvram, 0x30, RAM_size);
1306 NVRAM_set_byte(nvram, 0x34, boot_device);
1307 NVRAM_set_lword(nvram, 0x38, kernel_image);
1308 NVRAM_set_lword(nvram, 0x3C, kernel_size);
1310 /* XXX: put the cmdline in NVRAM too ? */
1311 strcpy(phys_ram_base + CMDLINE_ADDR, cmdline);
1312 NVRAM_set_lword(nvram, 0x40, CMDLINE_ADDR);
1313 NVRAM_set_lword(nvram, 0x44, strlen(cmdline));
1315 NVRAM_set_lword(nvram, 0x40, 0);
1316 NVRAM_set_lword(nvram, 0x44, 0);
1318 NVRAM_set_lword(nvram, 0x48, initrd_image);
1319 NVRAM_set_lword(nvram, 0x4C, initrd_size);
1320 NVRAM_set_lword(nvram, 0x50, NVRAM_image);
1322 NVRAM_set_word(nvram, 0x54, width);
1323 NVRAM_set_word(nvram, 0x56, height);
1324 NVRAM_set_word(nvram, 0x58, depth);
1325 crc = NVRAM_compute_crc(nvram, 0x00, 0xF8);
1326 NVRAM_set_word(nvram, 0xFC, crc);