2 * QEMU generic PowerPC hardware System Emulator
4 * Copyright (c) 2003-2007 Jocelyn Mayer
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
27 //#define PPC_DEBUG_IRQ
32 void ppc_set_irq (CPUState *env, int n_IRQ, int level)
35 env->pending_interrupts |= 1 << n_IRQ;
36 cpu_interrupt(env, CPU_INTERRUPT_HARD);
38 env->pending_interrupts &= ~(1 << n_IRQ);
39 if (env->pending_interrupts == 0)
40 cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
42 #if defined(PPC_DEBUG_IRQ)
43 if (loglevel & CPU_LOG_INT) {
44 fprintf(logfile, "%s: %p n_IRQ %d level %d => pending %08x req %08x\n",
45 __func__, env, n_IRQ, level,
46 env->pending_interrupts, env->interrupt_request);
51 /* PowerPC 6xx / 7xx internal IRQ controller */
52 static void ppc6xx_set_irq (void *opaque, int pin, int level)
54 CPUState *env = opaque;
57 #if defined(PPC_DEBUG_IRQ)
58 if (loglevel & CPU_LOG_INT) {
59 fprintf(logfile, "%s: env %p pin %d level %d\n", __func__,
63 cur_level = (env->irq_input_state >> pin) & 1;
64 /* Don't generate spurious events */
65 if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) {
67 case PPC6xx_INPUT_INT:
68 /* Level sensitive - active high */
69 #if defined(PPC_DEBUG_IRQ)
70 if (loglevel & CPU_LOG_INT) {
71 fprintf(logfile, "%s: set the external IRQ state to %d\n",
75 ppc_set_irq(env, PPC_INTERRUPT_EXT, level);
77 case PPC6xx_INPUT_SMI:
78 /* Level sensitive - active high */
79 #if defined(PPC_DEBUG_IRQ)
80 if (loglevel & CPU_LOG_INT) {
81 fprintf(logfile, "%s: set the SMI IRQ state to %d\n",
85 ppc_set_irq(env, PPC_INTERRUPT_SMI, level);
87 case PPC6xx_INPUT_MCP:
88 /* Negative edge sensitive */
89 /* XXX: TODO: actual reaction may depends on HID0 status
90 * 603/604/740/750: check HID0[EMCP]
92 if (cur_level == 1 && level == 0) {
93 #if defined(PPC_DEBUG_IRQ)
94 if (loglevel & CPU_LOG_INT) {
95 fprintf(logfile, "%s: raise machine check state\n",
99 ppc_set_irq(env, PPC_INTERRUPT_MCK, 1);
102 case PPC6xx_INPUT_CKSTP_IN:
103 /* Level sensitive - active low */
104 /* XXX: TODO: relay the signal to CKSTP_OUT pin */
106 #if defined(PPC_DEBUG_IRQ)
107 if (loglevel & CPU_LOG_INT) {
108 fprintf(logfile, "%s: stop the CPU\n", __func__);
113 #if defined(PPC_DEBUG_IRQ)
114 if (loglevel & CPU_LOG_INT) {
115 fprintf(logfile, "%s: restart the CPU\n", __func__);
121 case PPC6xx_INPUT_HRESET:
122 /* Level sensitive - active low */
125 #if defined(PPC_DEBUG_IRQ)
126 if (loglevel & CPU_LOG_INT) {
127 fprintf(logfile, "%s: reset the CPU\n", __func__);
134 case PPC6xx_INPUT_SRESET:
135 #if defined(PPC_DEBUG_IRQ)
136 if (loglevel & CPU_LOG_INT) {
137 fprintf(logfile, "%s: set the RESET IRQ state to %d\n",
141 ppc_set_irq(env, PPC_INTERRUPT_RESET, level);
144 /* Unknown pin - do nothing */
145 #if defined(PPC_DEBUG_IRQ)
146 if (loglevel & CPU_LOG_INT) {
147 fprintf(logfile, "%s: unknown IRQ pin %d\n", __func__, pin);
153 env->irq_input_state |= 1 << pin;
155 env->irq_input_state &= ~(1 << pin);
159 void ppc6xx_irq_init (CPUState *env)
161 env->irq_inputs = (void **)qemu_allocate_irqs(&ppc6xx_set_irq, env, 6);
164 /* PowerPC 405 internal IRQ controller */
165 static void ppc405_set_irq (void *opaque, int pin, int level)
167 CPUState *env = opaque;
170 #if defined(PPC_DEBUG_IRQ)
171 printf("%s: env %p pin %d level %d\n", __func__, env, pin, level);
173 cur_level = (env->irq_input_state >> pin) & 1;
174 /* Don't generate spurious events */
175 if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) {
177 case PPC405_INPUT_RESET_SYS:
178 /* XXX: TODO: reset all peripherals */
180 case PPC405_INPUT_RESET_CHIP:
181 /* XXX: TODO: reset on-chip peripherals */
183 case PPC405_INPUT_RESET_CORE:
184 /* XXX: TODO: update DBSR[MRR] */
187 #if defined(PPC_DEBUG_IRQ)
188 printf("%s: reset the CPU\n", __func__);
194 case PPC405_INPUT_CINT:
195 /* Level sensitive - active high */
196 #if defined(PPC_DEBUG_IRQ)
197 printf("%s: set the critical IRQ state to %d\n", __func__, level);
200 ppc_set_irq(env, PPC_INTERRUPT_RESET, level);
202 case PPC405_INPUT_INT:
203 /* Level sensitive - active high */
204 #if defined(PPC_DEBUG_IRQ)
205 if (loglevel & CPU_LOG_INT) {
206 fprintf(logfile, "%s: set the external IRQ state to %d\n",
210 ppc_set_irq(env, PPC_INTERRUPT_EXT, level);
212 case PPC405_INPUT_HALT:
213 /* Level sensitive - active low */
215 #if defined(PPC_DEBUG_IRQ)
216 if (loglevel & CPU_LOG_INT) {
217 fprintf(logfile, "%s: stop the CPU\n", __func__);
222 #if defined(PPC_DEBUG_IRQ)
223 if (loglevel & CPU_LOG_INT) {
224 fprintf(logfile, "%s: restart the CPU\n", __func__);
230 case PPC405_INPUT_DEBUG:
231 /* Level sensitive - active high */
232 #if defined(PPC_DEBUG_IRQ)
233 if (loglevel & CPU_LOG_INT) {
234 fprintf(logfile, "%s: set the external IRQ state to %d\n",
238 ppc_set_irq(env, EXCP_40x_DEBUG, level);
241 /* Unknown pin - do nothing */
242 #if defined(PPC_DEBUG_IRQ)
243 if (loglevel & CPU_LOG_INT) {
244 fprintf(logfile, "%s: unknown IRQ pin %d\n", __func__, pin);
250 env->irq_input_state |= 1 << pin;
252 env->irq_input_state &= ~(1 << pin);
256 void ppc405_irq_init (CPUState *env)
258 env->irq_inputs = (void **)qemu_allocate_irqs(&ppc405_set_irq, env, 7);
261 /*****************************************************************************/
262 /* PowerPC time base and decrementer emulation */
266 /* Time base management */
267 int64_t tb_offset; /* Compensation */
268 uint32_t tb_freq; /* TB frequency */
269 /* Decrementer management */
270 uint64_t decr_next; /* Tick for next decr interrupt */
271 struct QEMUTimer *decr_timer;
275 static inline uint64_t cpu_ppc_get_tb (ppc_tb_t *tb_env)
277 /* TB time in tb periods */
278 return muldiv64(qemu_get_clock(vm_clock) + tb_env->tb_offset,
279 tb_env->tb_freq, ticks_per_sec);
282 uint32_t cpu_ppc_load_tbl (CPUState *env)
284 ppc_tb_t *tb_env = env->tb_env;
287 tb = cpu_ppc_get_tb(tb_env);
290 static int last_time;
293 if (last_time != now) {
296 fprintf(logfile, "%s: tb=0x%016lx %d %08lx\n",
297 __func__, tb, now, tb_env->tb_offset);
303 return tb & 0xFFFFFFFF;
306 uint32_t cpu_ppc_load_tbu (CPUState *env)
308 ppc_tb_t *tb_env = env->tb_env;
311 tb = cpu_ppc_get_tb(tb_env);
314 fprintf(logfile, "%s: tb=0x%016lx\n", __func__, tb);
321 static void cpu_ppc_store_tb (ppc_tb_t *tb_env, uint64_t value)
323 tb_env->tb_offset = muldiv64(value, ticks_per_sec, tb_env->tb_freq)
324 - qemu_get_clock(vm_clock);
327 fprintf(logfile, "%s: tb=0x%016lx offset=%08x\n", __func__, value);
332 void cpu_ppc_store_tbu (CPUState *env, uint32_t value)
334 ppc_tb_t *tb_env = env->tb_env;
336 cpu_ppc_store_tb(tb_env,
337 ((uint64_t)value << 32) | cpu_ppc_load_tbl(env));
340 void cpu_ppc_store_tbl (CPUState *env, uint32_t value)
342 ppc_tb_t *tb_env = env->tb_env;
344 cpu_ppc_store_tb(tb_env,
345 ((uint64_t)cpu_ppc_load_tbu(env) << 32) | value);
348 uint32_t cpu_ppc_load_decr (CPUState *env)
350 ppc_tb_t *tb_env = env->tb_env;
354 diff = tb_env->decr_next - qemu_get_clock(vm_clock);
356 decr = muldiv64(diff, tb_env->tb_freq, ticks_per_sec);
358 decr = -muldiv64(-diff, tb_env->tb_freq, ticks_per_sec);
359 #if defined(DEBUG_TB)
361 fprintf(logfile, "%s: 0x%08x\n", __func__, decr);
368 /* When decrementer expires,
369 * all we need to do is generate or queue a CPU exception
371 static inline void cpu_ppc_decr_excp (CPUState *env)
376 fprintf(logfile, "raise decrementer exception\n");
379 ppc_set_irq(env, PPC_INTERRUPT_DECR, 1);
382 static void _cpu_ppc_store_decr (CPUState *env, uint32_t decr,
383 uint32_t value, int is_excp)
385 ppc_tb_t *tb_env = env->tb_env;
390 fprintf(logfile, "%s: 0x%08x => 0x%08x\n", __func__, decr, value);
393 now = qemu_get_clock(vm_clock);
394 next = now + muldiv64(value, ticks_per_sec, tb_env->tb_freq);
396 next += tb_env->decr_next - now;
399 tb_env->decr_next = next;
401 qemu_mod_timer(tb_env->decr_timer, next);
402 /* If we set a negative value and the decrementer was positive,
403 * raise an exception.
405 if ((value & 0x80000000) && !(decr & 0x80000000))
406 cpu_ppc_decr_excp(env);
409 void cpu_ppc_store_decr (CPUState *env, uint32_t value)
411 _cpu_ppc_store_decr(env, cpu_ppc_load_decr(env), value, 0);
414 static void cpu_ppc_decr_cb (void *opaque)
416 _cpu_ppc_store_decr(opaque, 0x00000000, 0xFFFFFFFF, 1);
419 /* Set up (once) timebase frequency (in Hz) */
420 ppc_tb_t *cpu_ppc_tb_init (CPUState *env, uint32_t freq)
424 tb_env = qemu_mallocz(sizeof(ppc_tb_t));
427 env->tb_env = tb_env;
428 if (tb_env->tb_freq == 0 || 1) {
429 tb_env->tb_freq = freq;
430 /* Create new timer */
432 qemu_new_timer(vm_clock, &cpu_ppc_decr_cb, env);
433 /* There is a bug in Linux 2.4 kernels:
434 * if a decrementer exception is pending when it enables msr_ee,
435 * it's not ready to handle it...
437 _cpu_ppc_store_decr(env, 0xFFFFFFFF, 0xFFFFFFFF, 0);
443 /* Specific helpers for POWER & PowerPC 601 RTC */
444 ppc_tb_t *cpu_ppc601_rtc_init (CPUState *env)
446 return cpu_ppc_tb_init(env, 7812500);
449 void cpu_ppc601_store_rtcu (CPUState *env, uint32_t value)
450 __attribute__ (( alias ("cpu_ppc_store_tbu") ));
452 uint32_t cpu_ppc601_load_rtcu (CPUState *env)
453 __attribute__ (( alias ("cpu_ppc_load_tbu") ));
455 void cpu_ppc601_store_rtcl (CPUState *env, uint32_t value)
457 cpu_ppc_store_tbl(env, value & 0x3FFFFF80);
460 uint32_t cpu_ppc601_load_rtcl (CPUState *env)
462 return cpu_ppc_load_tbl(env) & 0x3FFFFF80;
465 /*****************************************************************************/
466 /* Embedded PowerPC timers */
469 typedef struct ppcemb_timer_t ppcemb_timer_t;
470 struct ppcemb_timer_t {
471 uint64_t pit_reload; /* PIT auto-reload value */
472 uint64_t fit_next; /* Tick for next FIT interrupt */
473 struct QEMUTimer *fit_timer;
474 uint64_t wdt_next; /* Tick for next WDT interrupt */
475 struct QEMUTimer *wdt_timer;
478 /* Fixed interval timer */
479 static void cpu_4xx_fit_cb (void *opaque)
483 ppcemb_timer_t *ppcemb_timer;
487 tb_env = env->tb_env;
488 ppcemb_timer = tb_env->opaque;
489 now = qemu_get_clock(vm_clock);
490 switch ((env->spr[SPR_40x_TCR] >> 24) & 0x3) {
504 /* Cannot occur, but makes gcc happy */
507 next = now + muldiv64(next, ticks_per_sec, tb_env->tb_freq);
510 qemu_mod_timer(ppcemb_timer->fit_timer, next);
511 tb_env->decr_next = next;
512 env->spr[SPR_40x_TSR] |= 1 << 26;
513 if ((env->spr[SPR_40x_TCR] >> 23) & 0x1)
514 ppc_set_irq(env, PPC_INTERRUPT_FIT, 1);
516 fprintf(logfile, "%s: ir %d TCR " ADDRX " TSR " ADDRX "\n", __func__,
517 (int)((env->spr[SPR_40x_TCR] >> 23) & 0x1),
518 env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]);
522 /* Programmable interval timer */
523 static void cpu_4xx_pit_cb (void *opaque)
527 ppcemb_timer_t *ppcemb_timer;
531 tb_env = env->tb_env;
532 ppcemb_timer = tb_env->opaque;
533 now = qemu_get_clock(vm_clock);
534 if ((env->spr[SPR_40x_TCR] >> 22) & 0x1) {
536 next = now + muldiv64(ppcemb_timer->pit_reload,
537 ticks_per_sec, tb_env->tb_freq);
540 qemu_mod_timer(tb_env->decr_timer, next);
541 tb_env->decr_next = next;
543 env->spr[SPR_40x_TSR] |= 1 << 27;
544 if ((env->spr[SPR_40x_TCR] >> 26) & 0x1)
545 ppc_set_irq(env, PPC_INTERRUPT_PIT, 1);
547 fprintf(logfile, "%s: ar %d ir %d TCR " ADDRX " TSR " ADDRX " "
548 "%016" PRIx64 "\n", __func__,
549 (int)((env->spr[SPR_40x_TCR] >> 22) & 0x1),
550 (int)((env->spr[SPR_40x_TCR] >> 26) & 0x1),
551 env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR],
552 ppcemb_timer->pit_reload);
557 static void cpu_4xx_wdt_cb (void *opaque)
561 ppcemb_timer_t *ppcemb_timer;
565 tb_env = env->tb_env;
566 ppcemb_timer = tb_env->opaque;
567 now = qemu_get_clock(vm_clock);
568 switch ((env->spr[SPR_40x_TCR] >> 30) & 0x3) {
582 /* Cannot occur, but makes gcc happy */
585 next = now + muldiv64(next, ticks_per_sec, tb_env->tb_freq);
589 fprintf(logfile, "%s: TCR " ADDRX " TSR " ADDRX "\n", __func__,
590 env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]);
592 switch ((env->spr[SPR_40x_TSR] >> 30) & 0x3) {
595 qemu_mod_timer(ppcemb_timer->wdt_timer, next);
596 ppcemb_timer->wdt_next = next;
597 env->spr[SPR_40x_TSR] |= 1 << 31;
600 qemu_mod_timer(ppcemb_timer->wdt_timer, next);
601 ppcemb_timer->wdt_next = next;
602 env->spr[SPR_40x_TSR] |= 1 << 30;
603 if ((env->spr[SPR_40x_TCR] >> 27) & 0x1)
604 ppc_set_irq(env, PPC_INTERRUPT_WDT, 1);
607 env->spr[SPR_40x_TSR] &= ~0x30000000;
608 env->spr[SPR_40x_TSR] |= env->spr[SPR_40x_TCR] & 0x30000000;
609 switch ((env->spr[SPR_40x_TCR] >> 28) & 0x3) {
613 case 0x1: /* Core reset */
614 case 0x2: /* Chip reset */
615 case 0x3: /* System reset */
616 qemu_system_reset_request();
622 void store_40x_pit (CPUState *env, target_ulong val)
625 ppcemb_timer_t *ppcemb_timer;
628 tb_env = env->tb_env;
629 ppcemb_timer = tb_env->opaque;
631 fprintf(logfile, "%s %p %p\n", __func__, tb_env, ppcemb_timer);
633 ppcemb_timer->pit_reload = val;
637 fprintf(logfile, "%s: stop PIT\n", __func__);
639 qemu_del_timer(tb_env->decr_timer);
642 fprintf(logfile, "%s: start PIT 0x" ADDRX "\n", __func__, val);
644 now = qemu_get_clock(vm_clock);
645 next = now + muldiv64(val, ticks_per_sec, tb_env->tb_freq);
648 qemu_mod_timer(tb_env->decr_timer, next);
649 tb_env->decr_next = next;
653 target_ulong load_40x_pit (CPUState *env)
655 return cpu_ppc_load_decr(env);
658 void store_booke_tsr (CPUState *env, target_ulong val)
660 env->spr[SPR_40x_TSR] = val & 0xFC000000;
663 void store_booke_tcr (CPUState *env, target_ulong val)
665 /* We don't update timers now. Maybe we should... */
666 env->spr[SPR_40x_TCR] = val & 0xFF800000;
669 void ppc_emb_timers_init (CPUState *env)
672 ppcemb_timer_t *ppcemb_timer;
674 tb_env = env->tb_env;
675 ppcemb_timer = qemu_mallocz(sizeof(ppcemb_timer_t));
676 tb_env->opaque = ppcemb_timer;
678 fprintf(logfile, "%s %p %p\n", __func__, tb_env, ppcemb_timer);
679 if (ppcemb_timer != NULL) {
680 /* We use decr timer for PIT */
681 tb_env->decr_timer = qemu_new_timer(vm_clock, &cpu_4xx_pit_cb, env);
682 ppcemb_timer->fit_timer =
683 qemu_new_timer(vm_clock, &cpu_4xx_fit_cb, env);
684 ppcemb_timer->wdt_timer =
685 qemu_new_timer(vm_clock, &cpu_4xx_wdt_cb, env);
689 /*****************************************************************************/
690 /* Embedded PowerPC Device Control Registers */
691 typedef struct ppc_dcrn_t ppc_dcrn_t;
693 dcr_read_cb dcr_read;
694 dcr_write_cb dcr_write;
700 ppc_dcrn_t dcrn[DCRN_NB];
701 int (*read_error)(int dcrn);
702 int (*write_error)(int dcrn);
705 int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, target_ulong *valp)
709 if (dcrn < 0 || dcrn >= DCRN_NB)
711 dcr = &dcr_env->dcrn[dcrn];
712 if (dcr->dcr_read == NULL)
714 *valp = (*dcr->dcr_read)(dcr->opaque, dcrn);
719 if (dcr_env->read_error != NULL)
720 return (*dcr_env->read_error)(dcrn);
725 int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val)
729 if (dcrn < 0 || dcrn >= DCRN_NB)
731 dcr = &dcr_env->dcrn[dcrn];
732 if (dcr->dcr_write == NULL)
734 (*dcr->dcr_write)(dcr->opaque, dcrn, val);
739 if (dcr_env->write_error != NULL)
740 return (*dcr_env->write_error)(dcrn);
745 int ppc_dcr_register (CPUState *env, int dcrn, void *opaque,
746 dcr_read_cb dcr_read, dcr_write_cb dcr_write)
751 dcr_env = env->dcr_env;
754 if (dcrn < 0 || dcrn >= DCRN_NB)
756 dcr = &dcr_env->dcrn[dcrn];
757 if (dcr->opaque != NULL ||
758 dcr->dcr_read != NULL ||
759 dcr->dcr_write != NULL)
761 dcr->opaque = opaque;
762 dcr->dcr_read = dcr_read;
763 dcr->dcr_write = dcr_write;
768 int ppc_dcr_init (CPUState *env, int (*read_error)(int dcrn),
769 int (*write_error)(int dcrn))
773 dcr_env = qemu_mallocz(sizeof(ppc_dcr_t));
776 dcr_env->read_error = read_error;
777 dcr_env->write_error = write_error;
778 env->dcr_env = dcr_env;
785 /*****************************************************************************/
786 /* Handle system reset (for now, just stop emulation) */
787 void cpu_ppc_reset (CPUState *env)
789 printf("Reset asked... Stop emulation\n");
794 /*****************************************************************************/
796 void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val)
808 printf("Set loglevel to %04x\n", val);
809 cpu_set_log(val | 0x100);
814 /*****************************************************************************/
816 void NVRAM_set_byte (m48t59_t *nvram, uint32_t addr, uint8_t value)
818 m48t59_write(nvram, addr, value);
821 uint8_t NVRAM_get_byte (m48t59_t *nvram, uint32_t addr)
823 return m48t59_read(nvram, addr);
826 void NVRAM_set_word (m48t59_t *nvram, uint32_t addr, uint16_t value)
828 m48t59_write(nvram, addr, value >> 8);
829 m48t59_write(nvram, addr + 1, value & 0xFF);
832 uint16_t NVRAM_get_word (m48t59_t *nvram, uint32_t addr)
836 tmp = m48t59_read(nvram, addr) << 8;
837 tmp |= m48t59_read(nvram, addr + 1);
841 void NVRAM_set_lword (m48t59_t *nvram, uint32_t addr, uint32_t value)
843 m48t59_write(nvram, addr, value >> 24);
844 m48t59_write(nvram, addr + 1, (value >> 16) & 0xFF);
845 m48t59_write(nvram, addr + 2, (value >> 8) & 0xFF);
846 m48t59_write(nvram, addr + 3, value & 0xFF);
849 uint32_t NVRAM_get_lword (m48t59_t *nvram, uint32_t addr)
853 tmp = m48t59_read(nvram, addr) << 24;
854 tmp |= m48t59_read(nvram, addr + 1) << 16;
855 tmp |= m48t59_read(nvram, addr + 2) << 8;
856 tmp |= m48t59_read(nvram, addr + 3);
861 void NVRAM_set_string (m48t59_t *nvram, uint32_t addr,
862 const unsigned char *str, uint32_t max)
866 for (i = 0; i < max && str[i] != '\0'; i++) {
867 m48t59_write(nvram, addr + i, str[i]);
869 m48t59_write(nvram, addr + max - 1, '\0');
872 int NVRAM_get_string (m48t59_t *nvram, uint8_t *dst, uint16_t addr, int max)
877 for (i = 0; i < max; i++) {
878 dst[i] = NVRAM_get_byte(nvram, addr + i);
886 static uint16_t NVRAM_crc_update (uint16_t prev, uint16_t value)
889 uint16_t pd, pd1, pd2;
894 pd2 = ((pd >> 4) & 0x000F) ^ pd1;
895 tmp ^= (pd1 << 3) | (pd1 << 8);
896 tmp ^= pd2 | (pd2 << 7) | (pd2 << 12);
901 uint16_t NVRAM_compute_crc (m48t59_t *nvram, uint32_t start, uint32_t count)
904 uint16_t crc = 0xFFFF;
909 for (i = 0; i != count; i++) {
910 crc = NVRAM_crc_update(crc, NVRAM_get_word(nvram, start + i));
913 crc = NVRAM_crc_update(crc, NVRAM_get_byte(nvram, start + i) << 8);
919 #define CMDLINE_ADDR 0x017ff000
921 int PPC_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size,
922 const unsigned char *arch,
923 uint32_t RAM_size, int boot_device,
924 uint32_t kernel_image, uint32_t kernel_size,
926 uint32_t initrd_image, uint32_t initrd_size,
927 uint32_t NVRAM_image,
928 int width, int height, int depth)
932 /* Set parameters for Open Hack'Ware BIOS */
933 NVRAM_set_string(nvram, 0x00, "QEMU_BIOS", 16);
934 NVRAM_set_lword(nvram, 0x10, 0x00000002); /* structure v2 */
935 NVRAM_set_word(nvram, 0x14, NVRAM_size);
936 NVRAM_set_string(nvram, 0x20, arch, 16);
937 NVRAM_set_lword(nvram, 0x30, RAM_size);
938 NVRAM_set_byte(nvram, 0x34, boot_device);
939 NVRAM_set_lword(nvram, 0x38, kernel_image);
940 NVRAM_set_lword(nvram, 0x3C, kernel_size);
942 /* XXX: put the cmdline in NVRAM too ? */
943 strcpy(phys_ram_base + CMDLINE_ADDR, cmdline);
944 NVRAM_set_lword(nvram, 0x40, CMDLINE_ADDR);
945 NVRAM_set_lword(nvram, 0x44, strlen(cmdline));
947 NVRAM_set_lword(nvram, 0x40, 0);
948 NVRAM_set_lword(nvram, 0x44, 0);
950 NVRAM_set_lword(nvram, 0x48, initrd_image);
951 NVRAM_set_lword(nvram, 0x4C, initrd_size);
952 NVRAM_set_lword(nvram, 0x50, NVRAM_image);
954 NVRAM_set_word(nvram, 0x54, width);
955 NVRAM_set_word(nvram, 0x56, height);
956 NVRAM_set_word(nvram, 0x58, depth);
957 crc = NVRAM_compute_crc(nvram, 0x00, 0xF8);
958 NVRAM_set_word(nvram, 0xFC, crc);