2 * QEMU generic PowerPC hardware System Emulator
4 * Copyright (c) 2003-2007 Jocelyn Mayer
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
27 //#define PPC_DEBUG_IRQ
28 //#define PPC_DEBUG_TB
33 void ppc_set_irq (CPUState *env, int n_IRQ, int level)
36 env->pending_interrupts |= 1 << n_IRQ;
37 cpu_interrupt(env, CPU_INTERRUPT_HARD);
39 env->pending_interrupts &= ~(1 << n_IRQ);
40 if (env->pending_interrupts == 0)
41 cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
43 #if defined(PPC_DEBUG_IRQ)
44 if (loglevel & CPU_LOG_INT) {
45 fprintf(logfile, "%s: %p n_IRQ %d level %d => pending %08x req %08x\n",
46 __func__, env, n_IRQ, level,
47 env->pending_interrupts, env->interrupt_request);
52 /* PowerPC 6xx / 7xx internal IRQ controller */
53 static void ppc6xx_set_irq (void *opaque, int pin, int level)
55 CPUState *env = opaque;
58 #if defined(PPC_DEBUG_IRQ)
59 if (loglevel & CPU_LOG_INT) {
60 fprintf(logfile, "%s: env %p pin %d level %d\n", __func__,
64 cur_level = (env->irq_input_state >> pin) & 1;
65 /* Don't generate spurious events */
66 if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) {
68 case PPC6xx_INPUT_INT:
69 /* Level sensitive - active high */
70 #if defined(PPC_DEBUG_IRQ)
71 if (loglevel & CPU_LOG_INT) {
72 fprintf(logfile, "%s: set the external IRQ state to %d\n",
76 ppc_set_irq(env, PPC_INTERRUPT_EXT, level);
78 case PPC6xx_INPUT_SMI:
79 /* Level sensitive - active high */
80 #if defined(PPC_DEBUG_IRQ)
81 if (loglevel & CPU_LOG_INT) {
82 fprintf(logfile, "%s: set the SMI IRQ state to %d\n",
86 ppc_set_irq(env, PPC_INTERRUPT_SMI, level);
88 case PPC6xx_INPUT_MCP:
89 /* Negative edge sensitive */
90 /* XXX: TODO: actual reaction may depends on HID0 status
91 * 603/604/740/750: check HID0[EMCP]
93 if (cur_level == 1 && level == 0) {
94 #if defined(PPC_DEBUG_IRQ)
95 if (loglevel & CPU_LOG_INT) {
96 fprintf(logfile, "%s: raise machine check state\n",
100 ppc_set_irq(env, PPC_INTERRUPT_MCK, 1);
103 case PPC6xx_INPUT_CKSTP_IN:
104 /* Level sensitive - active low */
105 /* XXX: TODO: relay the signal to CKSTP_OUT pin */
107 #if defined(PPC_DEBUG_IRQ)
108 if (loglevel & CPU_LOG_INT) {
109 fprintf(logfile, "%s: stop the CPU\n", __func__);
114 #if defined(PPC_DEBUG_IRQ)
115 if (loglevel & CPU_LOG_INT) {
116 fprintf(logfile, "%s: restart the CPU\n", __func__);
122 case PPC6xx_INPUT_HRESET:
123 /* Level sensitive - active low */
126 #if defined(PPC_DEBUG_IRQ)
127 if (loglevel & CPU_LOG_INT) {
128 fprintf(logfile, "%s: reset the CPU\n", __func__);
135 case PPC6xx_INPUT_SRESET:
136 #if defined(PPC_DEBUG_IRQ)
137 if (loglevel & CPU_LOG_INT) {
138 fprintf(logfile, "%s: set the RESET IRQ state to %d\n",
142 ppc_set_irq(env, PPC_INTERRUPT_RESET, level);
145 /* Unknown pin - do nothing */
146 #if defined(PPC_DEBUG_IRQ)
147 if (loglevel & CPU_LOG_INT) {
148 fprintf(logfile, "%s: unknown IRQ pin %d\n", __func__, pin);
154 env->irq_input_state |= 1 << pin;
156 env->irq_input_state &= ~(1 << pin);
160 void ppc6xx_irq_init (CPUState *env)
162 env->irq_inputs = (void **)qemu_allocate_irqs(&ppc6xx_set_irq, env, 6);
165 /* PowerPC 970 internal IRQ controller */
166 static void ppc970_set_irq (void *opaque, int pin, int level)
168 CPUState *env = opaque;
171 #if defined(PPC_DEBUG_IRQ)
172 if (loglevel & CPU_LOG_INT) {
173 fprintf(logfile, "%s: env %p pin %d level %d\n", __func__,
177 cur_level = (env->irq_input_state >> pin) & 1;
178 /* Don't generate spurious events */
179 if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) {
181 case PPC970_INPUT_INT:
182 /* Level sensitive - active high */
183 #if defined(PPC_DEBUG_IRQ)
184 if (loglevel & CPU_LOG_INT) {
185 fprintf(logfile, "%s: set the external IRQ state to %d\n",
189 ppc_set_irq(env, PPC_INTERRUPT_EXT, level);
191 case PPC970_INPUT_THINT:
192 /* Level sensitive - active high */
193 #if defined(PPC_DEBUG_IRQ)
194 if (loglevel & CPU_LOG_INT) {
195 fprintf(logfile, "%s: set the SMI IRQ state to %d\n", __func__,
199 ppc_set_irq(env, PPC_INTERRUPT_THERM, level);
201 case PPC970_INPUT_MCP:
202 /* Negative edge sensitive */
203 /* XXX: TODO: actual reaction may depends on HID0 status
204 * 603/604/740/750: check HID0[EMCP]
206 if (cur_level == 1 && level == 0) {
207 #if defined(PPC_DEBUG_IRQ)
208 if (loglevel & CPU_LOG_INT) {
209 fprintf(logfile, "%s: raise machine check state\n",
213 ppc_set_irq(env, PPC_INTERRUPT_MCK, 1);
216 case PPC970_INPUT_CKSTP:
217 /* Level sensitive - active low */
218 /* XXX: TODO: relay the signal to CKSTP_OUT pin */
220 #if defined(PPC_DEBUG_IRQ)
221 if (loglevel & CPU_LOG_INT) {
222 fprintf(logfile, "%s: stop the CPU\n", __func__);
227 #if defined(PPC_DEBUG_IRQ)
228 if (loglevel & CPU_LOG_INT) {
229 fprintf(logfile, "%s: restart the CPU\n", __func__);
235 case PPC970_INPUT_HRESET:
236 /* Level sensitive - active low */
239 #if defined(PPC_DEBUG_IRQ)
240 if (loglevel & CPU_LOG_INT) {
241 fprintf(logfile, "%s: reset the CPU\n", __func__);
248 case PPC970_INPUT_SRESET:
249 #if defined(PPC_DEBUG_IRQ)
250 if (loglevel & CPU_LOG_INT) {
251 fprintf(logfile, "%s: set the RESET IRQ state to %d\n",
255 ppc_set_irq(env, PPC_INTERRUPT_RESET, level);
257 case PPC970_INPUT_TBEN:
258 #if defined(PPC_DEBUG_IRQ)
259 if (loglevel & CPU_LOG_INT) {
260 fprintf(logfile, "%s: set the TBEN state to %d\n", __func__,
267 /* Unknown pin - do nothing */
268 #if defined(PPC_DEBUG_IRQ)
269 if (loglevel & CPU_LOG_INT) {
270 fprintf(logfile, "%s: unknown IRQ pin %d\n", __func__, pin);
276 env->irq_input_state |= 1 << pin;
278 env->irq_input_state &= ~(1 << pin);
282 void ppc970_irq_init (CPUState *env)
284 env->irq_inputs = (void **)qemu_allocate_irqs(&ppc970_set_irq, env, 7);
287 /* PowerPC 405 internal IRQ controller */
288 static void ppc405_set_irq (void *opaque, int pin, int level)
290 CPUState *env = opaque;
293 #if defined(PPC_DEBUG_IRQ)
294 if (loglevel & CPU_LOG_INT) {
295 fprintf(logfile, "%s: env %p pin %d level %d\n", __func__,
299 cur_level = (env->irq_input_state >> pin) & 1;
300 /* Don't generate spurious events */
301 if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) {
303 case PPC405_INPUT_RESET_SYS:
305 #if defined(PPC_DEBUG_IRQ)
306 if (loglevel & CPU_LOG_INT) {
307 fprintf(logfile, "%s: reset the PowerPC system\n",
311 ppc40x_system_reset(env);
314 case PPC405_INPUT_RESET_CHIP:
316 #if defined(PPC_DEBUG_IRQ)
317 if (loglevel & CPU_LOG_INT) {
318 fprintf(logfile, "%s: reset the PowerPC chip\n", __func__);
321 ppc40x_chip_reset(env);
325 case PPC405_INPUT_RESET_CORE:
326 /* XXX: TODO: update DBSR[MRR] */
328 #if defined(PPC_DEBUG_IRQ)
329 if (loglevel & CPU_LOG_INT) {
330 fprintf(logfile, "%s: reset the PowerPC core\n", __func__);
333 ppc40x_core_reset(env);
336 case PPC405_INPUT_CINT:
337 /* Level sensitive - active high */
338 #if defined(PPC_DEBUG_IRQ)
339 if (loglevel & CPU_LOG_INT) {
340 fprintf(logfile, "%s: set the critical IRQ state to %d\n",
345 ppc_set_irq(env, PPC_INTERRUPT_RESET, level);
347 case PPC405_INPUT_INT:
348 /* Level sensitive - active high */
349 #if defined(PPC_DEBUG_IRQ)
350 if (loglevel & CPU_LOG_INT) {
351 fprintf(logfile, "%s: set the external IRQ state to %d\n",
355 ppc_set_irq(env, PPC_INTERRUPT_EXT, level);
357 case PPC405_INPUT_HALT:
358 /* Level sensitive - active low */
360 #if defined(PPC_DEBUG_IRQ)
361 if (loglevel & CPU_LOG_INT) {
362 fprintf(logfile, "%s: stop the CPU\n", __func__);
367 #if defined(PPC_DEBUG_IRQ)
368 if (loglevel & CPU_LOG_INT) {
369 fprintf(logfile, "%s: restart the CPU\n", __func__);
375 case PPC405_INPUT_DEBUG:
376 /* Level sensitive - active high */
377 #if defined(PPC_DEBUG_IRQ)
378 if (loglevel & CPU_LOG_INT) {
379 fprintf(logfile, "%s: set the debug pin state to %d\n",
383 ppc_set_irq(env, PPC_INTERRUPT_DEBUG, level);
386 /* Unknown pin - do nothing */
387 #if defined(PPC_DEBUG_IRQ)
388 if (loglevel & CPU_LOG_INT) {
389 fprintf(logfile, "%s: unknown IRQ pin %d\n", __func__, pin);
395 env->irq_input_state |= 1 << pin;
397 env->irq_input_state &= ~(1 << pin);
401 void ppc405_irq_init (CPUState *env)
403 env->irq_inputs = (void **)qemu_allocate_irqs(&ppc405_set_irq, env, 7);
406 /*****************************************************************************/
407 /* PowerPC time base and decrementer emulation */
409 /* Time base management */
410 int64_t tb_offset; /* Compensation */
411 int64_t atb_offset; /* Compensation */
412 uint32_t tb_freq; /* TB frequency */
413 /* Decrementer management */
414 uint64_t decr_next; /* Tick for next decr interrupt */
415 struct QEMUTimer *decr_timer;
416 #if defined(TARGET_PPC64H)
417 /* Hypervisor decrementer management */
418 uint64_t hdecr_next; /* Tick for next hdecr interrupt */
419 struct QEMUTimer *hdecr_timer;
426 static inline uint64_t cpu_ppc_get_tb (ppc_tb_t *tb_env, int64_t tb_offset)
428 /* TB time in tb periods */
429 return muldiv64(qemu_get_clock(vm_clock) + tb_env->tb_offset,
430 tb_env->tb_freq, ticks_per_sec);
433 uint32_t cpu_ppc_load_tbl (CPUState *env)
435 ppc_tb_t *tb_env = env->tb_env;
438 tb = cpu_ppc_get_tb(tb_env, tb_env->tb_offset);
439 #if defined(PPC_DEBUG_TB)
441 fprintf(logfile, "%s: tb=0x%016lx\n", __func__, tb);
445 return tb & 0xFFFFFFFF;
448 uint32_t cpu_ppc_load_tbu (CPUState *env)
450 ppc_tb_t *tb_env = env->tb_env;
453 tb = cpu_ppc_get_tb(tb_env, tb_env->tb_offset);
454 #if defined(PPC_DEBUG_TB)
456 fprintf(logfile, "%s: tb=0x%016lx\n", __func__, tb);
463 static inline void cpu_ppc_store_tb (ppc_tb_t *tb_env, int64_t *tb_offsetp,
466 *tb_offsetp = muldiv64(value, ticks_per_sec, tb_env->tb_freq)
467 - qemu_get_clock(vm_clock);
470 fprintf(logfile, "%s: tb=0x%016lx offset=%08lx\n", __func__, value,
476 void cpu_ppc_store_tbl (CPUState *env, uint32_t value)
478 ppc_tb_t *tb_env = env->tb_env;
481 tb = cpu_ppc_get_tb(tb_env, tb_env->tb_offset);
482 tb &= 0xFFFFFFFF00000000ULL;
483 cpu_ppc_store_tb(tb_env, &tb_env->tb_offset, tb | (uint64_t)value);
486 void cpu_ppc_store_tbu (CPUState *env, uint32_t value)
488 ppc_tb_t *tb_env = env->tb_env;
491 tb = cpu_ppc_get_tb(tb_env, tb_env->tb_offset);
492 tb &= 0x00000000FFFFFFFFULL;
493 cpu_ppc_store_tb(tb_env, &tb_env->tb_offset,
494 ((uint64_t)value << 32) | tb);
497 uint32_t cpu_ppc_load_atbl (CPUState *env)
499 ppc_tb_t *tb_env = env->tb_env;
502 tb = cpu_ppc_get_tb(tb_env, tb_env->atb_offset);
503 #if defined(PPC_DEBUG_TB)
505 fprintf(logfile, "%s: tb=0x%016lx\n", __func__, tb);
509 return tb & 0xFFFFFFFF;
512 uint32_t cpu_ppc_load_atbu (CPUState *env)
514 ppc_tb_t *tb_env = env->tb_env;
517 tb = cpu_ppc_get_tb(tb_env, tb_env->atb_offset);
518 #if defined(PPC_DEBUG_TB)
520 fprintf(logfile, "%s: tb=0x%016lx\n", __func__, tb);
527 void cpu_ppc_store_atbl (CPUState *env, uint32_t value)
529 ppc_tb_t *tb_env = env->tb_env;
532 tb = cpu_ppc_get_tb(tb_env, tb_env->atb_offset);
533 tb &= 0xFFFFFFFF00000000ULL;
534 cpu_ppc_store_tb(tb_env, &tb_env->atb_offset, tb | (uint64_t)value);
537 void cpu_ppc_store_atbu (CPUState *env, uint32_t value)
539 ppc_tb_t *tb_env = env->tb_env;
542 tb = cpu_ppc_get_tb(tb_env, tb_env->atb_offset);
543 tb &= 0x00000000FFFFFFFFULL;
544 cpu_ppc_store_tb(tb_env, &tb_env->atb_offset,
545 ((uint64_t)value << 32) | tb);
548 static inline uint32_t _cpu_ppc_load_decr (CPUState *env, uint64_t *next)
550 ppc_tb_t *tb_env = env->tb_env;
554 diff = tb_env->decr_next - qemu_get_clock(vm_clock);
556 decr = muldiv64(diff, tb_env->tb_freq, ticks_per_sec);
558 decr = -muldiv64(-diff, tb_env->tb_freq, ticks_per_sec);
559 #if defined(PPC_DEBUG_TB)
561 fprintf(logfile, "%s: 0x%08x\n", __func__, decr);
568 uint32_t cpu_ppc_load_decr (CPUState *env)
570 ppc_tb_t *tb_env = env->tb_env;
572 return _cpu_ppc_load_decr(env, &tb_env->decr_next);
575 #if defined(TARGET_PPC64H)
576 uint32_t cpu_ppc_load_hdecr (CPUState *env)
578 ppc_tb_t *tb_env = env->tb_env;
580 return _cpu_ppc_load_decr(env, &tb_env->hdecr_next);
583 uint64_t cpu_ppc_load_purr (CPUState *env)
585 ppc_tb_t *tb_env = env->tb_env;
588 diff = qemu_get_clock(vm_clock) - tb_env->purr_start;
590 return tb_env->purr_load + muldiv64(diff, tb_env->tb_freq, ticks_per_sec);
592 #endif /* defined(TARGET_PPC64H) */
594 /* When decrementer expires,
595 * all we need to do is generate or queue a CPU exception
597 static inline void cpu_ppc_decr_excp (CPUState *env)
602 fprintf(logfile, "raise decrementer exception\n");
605 ppc_set_irq(env, PPC_INTERRUPT_DECR, 1);
608 static inline void cpu_ppc_hdecr_excp (CPUState *env)
613 fprintf(logfile, "raise decrementer exception\n");
616 ppc_set_irq(env, PPC_INTERRUPT_HDECR, 1);
619 static void __cpu_ppc_store_decr (CPUState *env, uint64_t *nextp,
620 struct QEMUTimer *timer,
621 void (*raise_excp)(CPUState *),
622 uint32_t decr, uint32_t value,
625 ppc_tb_t *tb_env = env->tb_env;
630 fprintf(logfile, "%s: 0x%08x => 0x%08x\n", __func__, decr, value);
633 now = qemu_get_clock(vm_clock);
634 next = now + muldiv64(value, ticks_per_sec, tb_env->tb_freq);
636 next += *nextp - now;
641 qemu_mod_timer(timer, next);
642 /* If we set a negative value and the decrementer was positive,
643 * raise an exception.
645 if ((value & 0x80000000) && !(decr & 0x80000000))
650 static inline void _cpu_ppc_store_decr (CPUState *env, uint32_t decr,
651 uint32_t value, int is_excp)
653 ppc_tb_t *tb_env = env->tb_env;
655 __cpu_ppc_store_decr(env, &tb_env->decr_next, tb_env->decr_timer,
656 &cpu_ppc_decr_excp, decr, value, is_excp);
659 void cpu_ppc_store_decr (CPUState *env, uint32_t value)
661 _cpu_ppc_store_decr(env, cpu_ppc_load_decr(env), value, 0);
664 static void cpu_ppc_decr_cb (void *opaque)
666 _cpu_ppc_store_decr(opaque, 0x00000000, 0xFFFFFFFF, 1);
669 #if defined(TARGET_PPC64H)
670 static inline void _cpu_ppc_store_hdecr (CPUState *env, uint32_t hdecr,
671 uint32_t value, int is_excp)
673 ppc_tb_t *tb_env = env->tb_env;
675 __cpu_ppc_store_decr(env, &tb_env->hdecr_next, tb_env->hdecr_timer,
676 &cpu_ppc_hdecr_excp, hdecr, value, is_excp);
679 void cpu_ppc_store_hdecr (CPUState *env, uint32_t value)
681 _cpu_ppc_store_hdecr(env, cpu_ppc_load_hdecr(env), value, 0);
684 static void cpu_ppc_hdecr_cb (void *opaque)
686 _cpu_ppc_store_hdecr(opaque, 0x00000000, 0xFFFFFFFF, 1);
689 void cpu_ppc_store_purr (CPUState *env, uint64_t value)
691 ppc_tb_t *tb_env = env->tb_env;
693 tb_env->purr_load = value;
694 tb_env->purr_start = qemu_get_clock(vm_clock);
696 #endif /* defined(TARGET_PPC64H) */
698 static void cpu_ppc_set_tb_clk (void *opaque, uint32_t freq)
700 CPUState *env = opaque;
701 ppc_tb_t *tb_env = env->tb_env;
703 tb_env->tb_freq = freq;
704 /* There is a bug in Linux 2.4 kernels:
705 * if a decrementer exception is pending when it enables msr_ee at startup,
706 * it's not ready to handle it...
708 _cpu_ppc_store_decr(env, 0xFFFFFFFF, 0xFFFFFFFF, 0);
709 #if defined(TARGET_PPC64H)
710 _cpu_ppc_store_hdecr(env, 0xFFFFFFFF, 0xFFFFFFFF, 0);
711 cpu_ppc_store_purr(env, 0x0000000000000000ULL);
712 #endif /* defined(TARGET_PPC64H) */
715 /* Set up (once) timebase frequency (in Hz) */
716 clk_setup_cb cpu_ppc_tb_init (CPUState *env, uint32_t freq)
720 tb_env = qemu_mallocz(sizeof(ppc_tb_t));
723 env->tb_env = tb_env;
724 /* Create new timer */
725 tb_env->decr_timer = qemu_new_timer(vm_clock, &cpu_ppc_decr_cb, env);
726 #if defined(TARGET_PPC64H)
727 tb_env->hdecr_timer = qemu_new_timer(vm_clock, &cpu_ppc_hdecr_cb, env);
728 #endif /* defined(TARGET_PPC64H) */
729 cpu_ppc_set_tb_clk(env, freq);
731 return &cpu_ppc_set_tb_clk;
734 /* Specific helpers for POWER & PowerPC 601 RTC */
735 clk_setup_cb cpu_ppc601_rtc_init (CPUState *env)
737 return cpu_ppc_tb_init(env, 7812500);
740 void cpu_ppc601_store_rtcu (CPUState *env, uint32_t value)
741 __attribute__ (( alias ("cpu_ppc_store_tbu") ));
743 uint32_t cpu_ppc601_load_rtcu (CPUState *env)
744 __attribute__ (( alias ("cpu_ppc_load_tbu") ));
746 void cpu_ppc601_store_rtcl (CPUState *env, uint32_t value)
748 cpu_ppc_store_tbl(env, value & 0x3FFFFF80);
751 uint32_t cpu_ppc601_load_rtcl (CPUState *env)
753 return cpu_ppc_load_tbl(env) & 0x3FFFFF80;
756 /*****************************************************************************/
757 /* Embedded PowerPC timers */
760 typedef struct ppcemb_timer_t ppcemb_timer_t;
761 struct ppcemb_timer_t {
762 uint64_t pit_reload; /* PIT auto-reload value */
763 uint64_t fit_next; /* Tick for next FIT interrupt */
764 struct QEMUTimer *fit_timer;
765 uint64_t wdt_next; /* Tick for next WDT interrupt */
766 struct QEMUTimer *wdt_timer;
769 /* Fixed interval timer */
770 static void cpu_4xx_fit_cb (void *opaque)
774 ppcemb_timer_t *ppcemb_timer;
778 tb_env = env->tb_env;
779 ppcemb_timer = tb_env->opaque;
780 now = qemu_get_clock(vm_clock);
781 switch ((env->spr[SPR_40x_TCR] >> 24) & 0x3) {
795 /* Cannot occur, but makes gcc happy */
798 next = now + muldiv64(next, ticks_per_sec, tb_env->tb_freq);
801 qemu_mod_timer(ppcemb_timer->fit_timer, next);
802 env->spr[SPR_40x_TSR] |= 1 << 26;
803 if ((env->spr[SPR_40x_TCR] >> 23) & 0x1)
804 ppc_set_irq(env, PPC_INTERRUPT_FIT, 1);
807 fprintf(logfile, "%s: ir %d TCR " ADDRX " TSR " ADDRX "\n", __func__,
808 (int)((env->spr[SPR_40x_TCR] >> 23) & 0x1),
809 env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]);
814 /* Programmable interval timer */
815 static void start_stop_pit (CPUState *env, ppc_tb_t *tb_env, int is_excp)
817 ppcemb_timer_t *ppcemb_timer;
820 ppcemb_timer = tb_env->opaque;
821 if (ppcemb_timer->pit_reload <= 1 ||
822 !((env->spr[SPR_40x_TCR] >> 26) & 0x1) ||
823 (is_excp && !((env->spr[SPR_40x_TCR] >> 22) & 0x1))) {
827 fprintf(logfile, "%s: stop PIT\n", __func__);
830 qemu_del_timer(tb_env->decr_timer);
834 fprintf(logfile, "%s: start PIT 0x" REGX "\n",
835 __func__, ppcemb_timer->pit_reload);
838 now = qemu_get_clock(vm_clock);
839 next = now + muldiv64(ppcemb_timer->pit_reload,
840 ticks_per_sec, tb_env->tb_freq);
842 next += tb_env->decr_next - now;
845 qemu_mod_timer(tb_env->decr_timer, next);
846 tb_env->decr_next = next;
850 static void cpu_4xx_pit_cb (void *opaque)
854 ppcemb_timer_t *ppcemb_timer;
857 tb_env = env->tb_env;
858 ppcemb_timer = tb_env->opaque;
859 env->spr[SPR_40x_TSR] |= 1 << 27;
860 if ((env->spr[SPR_40x_TCR] >> 26) & 0x1)
861 ppc_set_irq(env, PPC_INTERRUPT_PIT, 1);
862 start_stop_pit(env, tb_env, 1);
865 fprintf(logfile, "%s: ar %d ir %d TCR " ADDRX " TSR " ADDRX " "
866 "%016" PRIx64 "\n", __func__,
867 (int)((env->spr[SPR_40x_TCR] >> 22) & 0x1),
868 (int)((env->spr[SPR_40x_TCR] >> 26) & 0x1),
869 env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR],
870 ppcemb_timer->pit_reload);
876 static void cpu_4xx_wdt_cb (void *opaque)
880 ppcemb_timer_t *ppcemb_timer;
884 tb_env = env->tb_env;
885 ppcemb_timer = tb_env->opaque;
886 now = qemu_get_clock(vm_clock);
887 switch ((env->spr[SPR_40x_TCR] >> 30) & 0x3) {
901 /* Cannot occur, but makes gcc happy */
904 next = now + muldiv64(next, ticks_per_sec, tb_env->tb_freq);
909 fprintf(logfile, "%s: TCR " ADDRX " TSR " ADDRX "\n", __func__,
910 env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]);
913 switch ((env->spr[SPR_40x_TSR] >> 30) & 0x3) {
916 qemu_mod_timer(ppcemb_timer->wdt_timer, next);
917 ppcemb_timer->wdt_next = next;
918 env->spr[SPR_40x_TSR] |= 1 << 31;
921 qemu_mod_timer(ppcemb_timer->wdt_timer, next);
922 ppcemb_timer->wdt_next = next;
923 env->spr[SPR_40x_TSR] |= 1 << 30;
924 if ((env->spr[SPR_40x_TCR] >> 27) & 0x1)
925 ppc_set_irq(env, PPC_INTERRUPT_WDT, 1);
928 env->spr[SPR_40x_TSR] &= ~0x30000000;
929 env->spr[SPR_40x_TSR] |= env->spr[SPR_40x_TCR] & 0x30000000;
930 switch ((env->spr[SPR_40x_TCR] >> 28) & 0x3) {
934 case 0x1: /* Core reset */
935 ppc40x_core_reset(env);
937 case 0x2: /* Chip reset */
938 ppc40x_chip_reset(env);
940 case 0x3: /* System reset */
941 ppc40x_system_reset(env);
947 void store_40x_pit (CPUState *env, target_ulong val)
950 ppcemb_timer_t *ppcemb_timer;
952 tb_env = env->tb_env;
953 ppcemb_timer = tb_env->opaque;
956 fprintf(logfile, "%s %p %p\n", __func__, tb_env, ppcemb_timer);
959 ppcemb_timer->pit_reload = val;
960 start_stop_pit(env, tb_env, 0);
963 target_ulong load_40x_pit (CPUState *env)
965 return cpu_ppc_load_decr(env);
968 void store_booke_tsr (CPUState *env, target_ulong val)
972 fprintf(logfile, "%s: val=" ADDRX "\n", __func__, val);
975 env->spr[SPR_40x_TSR] &= ~(val & 0xFC000000);
976 if (val & 0x80000000)
977 ppc_set_irq(env, PPC_INTERRUPT_PIT, 0);
980 void store_booke_tcr (CPUState *env, target_ulong val)
984 tb_env = env->tb_env;
987 fprintf(logfile, "%s: val=" ADDRX "\n", __func__, val);
990 env->spr[SPR_40x_TCR] = val & 0xFFC00000;
991 start_stop_pit(env, tb_env, 1);
995 static void ppc_emb_set_tb_clk (void *opaque, uint32_t freq)
997 CPUState *env = opaque;
998 ppc_tb_t *tb_env = env->tb_env;
1001 if (loglevel != 0) {
1002 fprintf(logfile, "%s set new frequency to %u\n", __func__, freq);
1005 tb_env->tb_freq = freq;
1006 /* XXX: we should also update all timers */
1009 clk_setup_cb ppc_emb_timers_init (CPUState *env, uint32_t freq)
1012 ppcemb_timer_t *ppcemb_timer;
1014 tb_env = qemu_mallocz(sizeof(ppc_tb_t));
1015 if (tb_env == NULL) {
1018 env->tb_env = tb_env;
1019 ppcemb_timer = qemu_mallocz(sizeof(ppcemb_timer_t));
1020 tb_env->tb_freq = freq;
1021 tb_env->opaque = ppcemb_timer;
1023 if (loglevel != 0) {
1024 fprintf(logfile, "%s %p %p %p\n", __func__, tb_env, ppcemb_timer,
1025 &ppc_emb_set_tb_clk);
1028 if (ppcemb_timer != NULL) {
1029 /* We use decr timer for PIT */
1030 tb_env->decr_timer = qemu_new_timer(vm_clock, &cpu_4xx_pit_cb, env);
1031 ppcemb_timer->fit_timer =
1032 qemu_new_timer(vm_clock, &cpu_4xx_fit_cb, env);
1033 ppcemb_timer->wdt_timer =
1034 qemu_new_timer(vm_clock, &cpu_4xx_wdt_cb, env);
1037 return &ppc_emb_set_tb_clk;
1040 /*****************************************************************************/
1041 /* Embedded PowerPC Device Control Registers */
1042 typedef struct ppc_dcrn_t ppc_dcrn_t;
1044 dcr_read_cb dcr_read;
1045 dcr_write_cb dcr_write;
1049 /* XXX: on 460, DCR addresses are 32 bits wide,
1050 * using DCRIPR to get the 22 upper bits of the DCR address
1052 #define DCRN_NB 1024
1054 ppc_dcrn_t dcrn[DCRN_NB];
1055 int (*read_error)(int dcrn);
1056 int (*write_error)(int dcrn);
1059 int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, target_ulong *valp)
1063 if (dcrn < 0 || dcrn >= DCRN_NB)
1065 dcr = &dcr_env->dcrn[dcrn];
1066 if (dcr->dcr_read == NULL)
1068 *valp = (*dcr->dcr_read)(dcr->opaque, dcrn);
1073 if (dcr_env->read_error != NULL)
1074 return (*dcr_env->read_error)(dcrn);
1079 int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val)
1083 if (dcrn < 0 || dcrn >= DCRN_NB)
1085 dcr = &dcr_env->dcrn[dcrn];
1086 if (dcr->dcr_write == NULL)
1088 (*dcr->dcr_write)(dcr->opaque, dcrn, val);
1093 if (dcr_env->write_error != NULL)
1094 return (*dcr_env->write_error)(dcrn);
1099 int ppc_dcr_register (CPUState *env, int dcrn, void *opaque,
1100 dcr_read_cb dcr_read, dcr_write_cb dcr_write)
1105 dcr_env = env->dcr_env;
1106 if (dcr_env == NULL)
1108 if (dcrn < 0 || dcrn >= DCRN_NB)
1110 dcr = &dcr_env->dcrn[dcrn];
1111 if (dcr->opaque != NULL ||
1112 dcr->dcr_read != NULL ||
1113 dcr->dcr_write != NULL)
1115 dcr->opaque = opaque;
1116 dcr->dcr_read = dcr_read;
1117 dcr->dcr_write = dcr_write;
1122 int ppc_dcr_init (CPUState *env, int (*read_error)(int dcrn),
1123 int (*write_error)(int dcrn))
1127 dcr_env = qemu_mallocz(sizeof(ppc_dcr_t));
1128 if (dcr_env == NULL)
1130 dcr_env->read_error = read_error;
1131 dcr_env->write_error = write_error;
1132 env->dcr_env = dcr_env;
1139 /*****************************************************************************/
1140 /* Handle system reset (for now, just stop emulation) */
1141 void cpu_ppc_reset (CPUState *env)
1143 printf("Reset asked... Stop emulation\n");
1148 /*****************************************************************************/
1150 void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val)
1162 printf("Set loglevel to %04x\n", val);
1163 cpu_set_log(val | 0x100);
1168 /*****************************************************************************/
1170 void NVRAM_set_byte (m48t59_t *nvram, uint32_t addr, uint8_t value)
1172 m48t59_write(nvram, addr, value);
1175 uint8_t NVRAM_get_byte (m48t59_t *nvram, uint32_t addr)
1177 return m48t59_read(nvram, addr);
1180 void NVRAM_set_word (m48t59_t *nvram, uint32_t addr, uint16_t value)
1182 m48t59_write(nvram, addr, value >> 8);
1183 m48t59_write(nvram, addr + 1, value & 0xFF);
1186 uint16_t NVRAM_get_word (m48t59_t *nvram, uint32_t addr)
1190 tmp = m48t59_read(nvram, addr) << 8;
1191 tmp |= m48t59_read(nvram, addr + 1);
1195 void NVRAM_set_lword (m48t59_t *nvram, uint32_t addr, uint32_t value)
1197 m48t59_write(nvram, addr, value >> 24);
1198 m48t59_write(nvram, addr + 1, (value >> 16) & 0xFF);
1199 m48t59_write(nvram, addr + 2, (value >> 8) & 0xFF);
1200 m48t59_write(nvram, addr + 3, value & 0xFF);
1203 uint32_t NVRAM_get_lword (m48t59_t *nvram, uint32_t addr)
1207 tmp = m48t59_read(nvram, addr) << 24;
1208 tmp |= m48t59_read(nvram, addr + 1) << 16;
1209 tmp |= m48t59_read(nvram, addr + 2) << 8;
1210 tmp |= m48t59_read(nvram, addr + 3);
1215 void NVRAM_set_string (m48t59_t *nvram, uint32_t addr,
1216 const unsigned char *str, uint32_t max)
1220 for (i = 0; i < max && str[i] != '\0'; i++) {
1221 m48t59_write(nvram, addr + i, str[i]);
1223 m48t59_write(nvram, addr + max - 1, '\0');
1226 int NVRAM_get_string (m48t59_t *nvram, uint8_t *dst, uint16_t addr, int max)
1230 memset(dst, 0, max);
1231 for (i = 0; i < max; i++) {
1232 dst[i] = NVRAM_get_byte(nvram, addr + i);
1240 static uint16_t NVRAM_crc_update (uint16_t prev, uint16_t value)
1243 uint16_t pd, pd1, pd2;
1248 pd2 = ((pd >> 4) & 0x000F) ^ pd1;
1249 tmp ^= (pd1 << 3) | (pd1 << 8);
1250 tmp ^= pd2 | (pd2 << 7) | (pd2 << 12);
1255 uint16_t NVRAM_compute_crc (m48t59_t *nvram, uint32_t start, uint32_t count)
1258 uint16_t crc = 0xFFFF;
1263 for (i = 0; i != count; i++) {
1264 crc = NVRAM_crc_update(crc, NVRAM_get_word(nvram, start + i));
1267 crc = NVRAM_crc_update(crc, NVRAM_get_byte(nvram, start + i) << 8);
1273 #define CMDLINE_ADDR 0x017ff000
1275 int PPC_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size,
1276 const unsigned char *arch,
1277 uint32_t RAM_size, int boot_device,
1278 uint32_t kernel_image, uint32_t kernel_size,
1279 const char *cmdline,
1280 uint32_t initrd_image, uint32_t initrd_size,
1281 uint32_t NVRAM_image,
1282 int width, int height, int depth)
1286 /* Set parameters for Open Hack'Ware BIOS */
1287 NVRAM_set_string(nvram, 0x00, "QEMU_BIOS", 16);
1288 NVRAM_set_lword(nvram, 0x10, 0x00000002); /* structure v2 */
1289 NVRAM_set_word(nvram, 0x14, NVRAM_size);
1290 NVRAM_set_string(nvram, 0x20, arch, 16);
1291 NVRAM_set_lword(nvram, 0x30, RAM_size);
1292 NVRAM_set_byte(nvram, 0x34, boot_device);
1293 NVRAM_set_lword(nvram, 0x38, kernel_image);
1294 NVRAM_set_lword(nvram, 0x3C, kernel_size);
1296 /* XXX: put the cmdline in NVRAM too ? */
1297 strcpy(phys_ram_base + CMDLINE_ADDR, cmdline);
1298 NVRAM_set_lword(nvram, 0x40, CMDLINE_ADDR);
1299 NVRAM_set_lword(nvram, 0x44, strlen(cmdline));
1301 NVRAM_set_lword(nvram, 0x40, 0);
1302 NVRAM_set_lword(nvram, 0x44, 0);
1304 NVRAM_set_lword(nvram, 0x48, initrd_image);
1305 NVRAM_set_lword(nvram, 0x4C, initrd_size);
1306 NVRAM_set_lword(nvram, 0x50, NVRAM_image);
1308 NVRAM_set_word(nvram, 0x54, width);
1309 NVRAM_set_word(nvram, 0x56, height);
1310 NVRAM_set_word(nvram, 0x58, depth);
1311 crc = NVRAM_compute_crc(nvram, 0x00, 0xF8);
1312 NVRAM_set_word(nvram, 0xFC, crc);