2 * QEMU generic PowerPC hardware System Emulator
4 * Copyright (c) 2003-2007 Jocelyn Mayer
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
27 //#define PPC_DEBUG_IRQ
32 void ppc_set_irq (CPUState *env, int n_IRQ, int level)
35 env->pending_interrupts |= 1 << n_IRQ;
36 cpu_interrupt(env, CPU_INTERRUPT_HARD);
38 env->pending_interrupts &= ~(1 << n_IRQ);
39 if (env->pending_interrupts == 0)
40 cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
42 #if defined(PPC_DEBUG_IRQ)
43 if (loglevel & CPU_LOG_INT) {
44 fprintf(logfile, "%s: %p n_IRQ %d level %d => pending %08x req %08x\n",
45 __func__, env, n_IRQ, level,
46 env->pending_interrupts, env->interrupt_request);
51 /* PowerPC 6xx / 7xx internal IRQ controller */
52 static void ppc6xx_set_irq (void *opaque, int pin, int level)
54 CPUState *env = opaque;
57 #if defined(PPC_DEBUG_IRQ)
58 if (loglevel & CPU_LOG_INT) {
59 fprintf(logfile, "%s: env %p pin %d level %d\n", __func__,
63 cur_level = (env->irq_input_state >> pin) & 1;
64 /* Don't generate spurious events */
65 if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) {
67 case PPC6xx_INPUT_INT:
68 /* Level sensitive - active high */
69 #if defined(PPC_DEBUG_IRQ)
70 if (loglevel & CPU_LOG_INT) {
71 fprintf(logfile, "%s: set the external IRQ state to %d\n",
75 ppc_set_irq(env, PPC_INTERRUPT_EXT, level);
77 case PPC6xx_INPUT_SMI:
78 /* Level sensitive - active high */
79 #if defined(PPC_DEBUG_IRQ)
80 if (loglevel & CPU_LOG_INT) {
81 fprintf(logfile, "%s: set the SMI IRQ state to %d\n",
85 ppc_set_irq(env, PPC_INTERRUPT_SMI, level);
87 case PPC6xx_INPUT_MCP:
88 /* Negative edge sensitive */
89 /* XXX: TODO: actual reaction may depends on HID0 status
90 * 603/604/740/750: check HID0[EMCP]
92 if (cur_level == 1 && level == 0) {
93 #if defined(PPC_DEBUG_IRQ)
94 if (loglevel & CPU_LOG_INT) {
95 fprintf(logfile, "%s: raise machine check state\n",
99 ppc_set_irq(env, PPC_INTERRUPT_MCK, 1);
102 case PPC6xx_INPUT_CKSTP_IN:
103 /* Level sensitive - active low */
104 /* XXX: TODO: relay the signal to CKSTP_OUT pin */
106 #if defined(PPC_DEBUG_IRQ)
107 if (loglevel & CPU_LOG_INT) {
108 fprintf(logfile, "%s: stop the CPU\n", __func__);
113 #if defined(PPC_DEBUG_IRQ)
114 if (loglevel & CPU_LOG_INT) {
115 fprintf(logfile, "%s: restart the CPU\n", __func__);
121 case PPC6xx_INPUT_HRESET:
122 /* Level sensitive - active low */
125 #if defined(PPC_DEBUG_IRQ)
126 if (loglevel & CPU_LOG_INT) {
127 fprintf(logfile, "%s: reset the CPU\n", __func__);
134 case PPC6xx_INPUT_SRESET:
135 #if defined(PPC_DEBUG_IRQ)
136 if (loglevel & CPU_LOG_INT) {
137 fprintf(logfile, "%s: set the RESET IRQ state to %d\n",
141 ppc_set_irq(env, PPC_INTERRUPT_RESET, level);
144 /* Unknown pin - do nothing */
145 #if defined(PPC_DEBUG_IRQ)
146 if (loglevel & CPU_LOG_INT) {
147 fprintf(logfile, "%s: unknown IRQ pin %d\n", __func__, pin);
153 env->irq_input_state |= 1 << pin;
155 env->irq_input_state &= ~(1 << pin);
159 void ppc6xx_irq_init (CPUState *env)
161 env->irq_inputs = (void **)qemu_allocate_irqs(&ppc6xx_set_irq, env, 6);
164 /* PowerPC 970 internal IRQ controller */
165 static void ppc970_set_irq (void *opaque, int pin, int level)
167 CPUState *env = opaque;
170 #if defined(PPC_DEBUG_IRQ)
171 if (loglevel & CPU_LOG_INT) {
172 fprintf(logfile, "%s: env %p pin %d level %d\n", __func__,
176 cur_level = (env->irq_input_state >> pin) & 1;
177 /* Don't generate spurious events */
178 if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) {
180 case PPC970_INPUT_INT:
181 /* Level sensitive - active high */
182 #if defined(PPC_DEBUG_IRQ)
183 if (loglevel & CPU_LOG_INT) {
184 fprintf(logfile, "%s: set the external IRQ state to %d\n",
188 ppc_set_irq(env, PPC_INTERRUPT_EXT, level);
190 case PPC970_INPUT_THINT:
191 /* Level sensitive - active high */
192 #if defined(PPC_DEBUG_IRQ)
193 if (loglevel & CPU_LOG_INT) {
194 fprintf(logfile, "%s: set the SMI IRQ state to %d\n", __func__,
198 ppc_set_irq(env, PPC_INTERRUPT_THERM, level);
200 case PPC970_INPUT_MCP:
201 /* Negative edge sensitive */
202 /* XXX: TODO: actual reaction may depends on HID0 status
203 * 603/604/740/750: check HID0[EMCP]
205 if (cur_level == 1 && level == 0) {
206 #if defined(PPC_DEBUG_IRQ)
207 if (loglevel & CPU_LOG_INT) {
208 fprintf(logfile, "%s: raise machine check state\n",
212 ppc_set_irq(env, PPC_INTERRUPT_MCK, 1);
215 case PPC970_INPUT_CKSTP:
216 /* Level sensitive - active low */
217 /* XXX: TODO: relay the signal to CKSTP_OUT pin */
219 #if defined(PPC_DEBUG_IRQ)
220 if (loglevel & CPU_LOG_INT) {
221 fprintf(logfile, "%s: stop the CPU\n", __func__);
226 #if defined(PPC_DEBUG_IRQ)
227 if (loglevel & CPU_LOG_INT) {
228 fprintf(logfile, "%s: restart the CPU\n", __func__);
234 case PPC970_INPUT_HRESET:
235 /* Level sensitive - active low */
238 #if defined(PPC_DEBUG_IRQ)
239 if (loglevel & CPU_LOG_INT) {
240 fprintf(logfile, "%s: reset the CPU\n", __func__);
247 case PPC970_INPUT_SRESET:
248 #if defined(PPC_DEBUG_IRQ)
249 if (loglevel & CPU_LOG_INT) {
250 fprintf(logfile, "%s: set the RESET IRQ state to %d\n",
254 ppc_set_irq(env, PPC_INTERRUPT_RESET, level);
256 case PPC970_INPUT_TBEN:
257 #if defined(PPC_DEBUG_IRQ)
258 if (loglevel & CPU_LOG_INT) {
259 fprintf(logfile, "%s: set the TBEN state to %d\n", __func__,
266 /* Unknown pin - do nothing */
267 #if defined(PPC_DEBUG_IRQ)
268 if (loglevel & CPU_LOG_INT) {
269 fprintf(logfile, "%s: unknown IRQ pin %d\n", __func__, pin);
275 env->irq_input_state |= 1 << pin;
277 env->irq_input_state &= ~(1 << pin);
281 void ppc970_irq_init (CPUState *env)
283 env->irq_inputs = (void **)qemu_allocate_irqs(&ppc970_set_irq, env, 7);
286 /* PowerPC 405 internal IRQ controller */
287 static void ppc405_set_irq (void *opaque, int pin, int level)
289 CPUState *env = opaque;
292 #if defined(PPC_DEBUG_IRQ)
293 if (loglevel & CPU_LOG_INT) {
294 fprintf(logfile, "%s: env %p pin %d level %d\n", __func__,
298 cur_level = (env->irq_input_state >> pin) & 1;
299 /* Don't generate spurious events */
300 if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) {
302 case PPC405_INPUT_RESET_SYS:
304 #if defined(PPC_DEBUG_IRQ)
305 if (loglevel & CPU_LOG_INT) {
306 fprintf(logfile, "%s: reset the PowerPC system\n",
310 ppc40x_system_reset(env);
313 case PPC405_INPUT_RESET_CHIP:
315 #if defined(PPC_DEBUG_IRQ)
316 if (loglevel & CPU_LOG_INT) {
317 fprintf(logfile, "%s: reset the PowerPC chip\n", __func__);
320 ppc40x_chip_reset(env);
324 case PPC405_INPUT_RESET_CORE:
325 /* XXX: TODO: update DBSR[MRR] */
327 #if defined(PPC_DEBUG_IRQ)
328 if (loglevel & CPU_LOG_INT) {
329 fprintf(logfile, "%s: reset the PowerPC core\n", __func__);
332 ppc40x_core_reset(env);
335 case PPC405_INPUT_CINT:
336 /* Level sensitive - active high */
337 #if defined(PPC_DEBUG_IRQ)
338 if (loglevel & CPU_LOG_INT) {
339 fprintf(logfile, "%s: set the critical IRQ state to %d\n",
344 ppc_set_irq(env, PPC_INTERRUPT_RESET, level);
346 case PPC405_INPUT_INT:
347 /* Level sensitive - active high */
348 #if defined(PPC_DEBUG_IRQ)
349 if (loglevel & CPU_LOG_INT) {
350 fprintf(logfile, "%s: set the external IRQ state to %d\n",
354 ppc_set_irq(env, PPC_INTERRUPT_EXT, level);
356 case PPC405_INPUT_HALT:
357 /* Level sensitive - active low */
359 #if defined(PPC_DEBUG_IRQ)
360 if (loglevel & CPU_LOG_INT) {
361 fprintf(logfile, "%s: stop the CPU\n", __func__);
366 #if defined(PPC_DEBUG_IRQ)
367 if (loglevel & CPU_LOG_INT) {
368 fprintf(logfile, "%s: restart the CPU\n", __func__);
374 case PPC405_INPUT_DEBUG:
375 /* Level sensitive - active high */
376 #if defined(PPC_DEBUG_IRQ)
377 if (loglevel & CPU_LOG_INT) {
378 fprintf(logfile, "%s: set the external IRQ state to %d\n",
382 ppc_set_irq(env, EXCP_40x_DEBUG, level);
385 /* Unknown pin - do nothing */
386 #if defined(PPC_DEBUG_IRQ)
387 if (loglevel & CPU_LOG_INT) {
388 fprintf(logfile, "%s: unknown IRQ pin %d\n", __func__, pin);
394 env->irq_input_state |= 1 << pin;
396 env->irq_input_state &= ~(1 << pin);
400 void ppc405_irq_init (CPUState *env)
402 env->irq_inputs = (void **)qemu_allocate_irqs(&ppc405_set_irq, env, 7);
405 /*****************************************************************************/
406 /* PowerPC time base and decrementer emulation */
410 /* Time base management */
411 int64_t tb_offset; /* Compensation */
412 uint32_t tb_freq; /* TB frequency */
413 /* Decrementer management */
414 uint64_t decr_next; /* Tick for next decr interrupt */
415 struct QEMUTimer *decr_timer;
419 static inline uint64_t cpu_ppc_get_tb (ppc_tb_t *tb_env)
421 /* TB time in tb periods */
422 return muldiv64(qemu_get_clock(vm_clock) + tb_env->tb_offset,
423 tb_env->tb_freq, ticks_per_sec);
426 uint32_t cpu_ppc_load_tbl (CPUState *env)
428 ppc_tb_t *tb_env = env->tb_env;
431 tb = cpu_ppc_get_tb(tb_env);
434 static int last_time;
437 if (last_time != now) {
440 fprintf(logfile, "%s: tb=0x%016lx %d %08lx\n",
441 __func__, tb, now, tb_env->tb_offset);
447 return tb & 0xFFFFFFFF;
450 uint32_t cpu_ppc_load_tbu (CPUState *env)
452 ppc_tb_t *tb_env = env->tb_env;
455 tb = cpu_ppc_get_tb(tb_env);
458 fprintf(logfile, "%s: tb=0x%016lx\n", __func__, tb);
465 static void cpu_ppc_store_tb (ppc_tb_t *tb_env, uint64_t value)
467 tb_env->tb_offset = muldiv64(value, ticks_per_sec, tb_env->tb_freq)
468 - qemu_get_clock(vm_clock);
471 fprintf(logfile, "%s: tb=0x%016lx offset=%08x\n", __func__, value);
476 void cpu_ppc_store_tbu (CPUState *env, uint32_t value)
478 ppc_tb_t *tb_env = env->tb_env;
480 cpu_ppc_store_tb(tb_env,
481 ((uint64_t)value << 32) | cpu_ppc_load_tbl(env));
484 void cpu_ppc_store_tbl (CPUState *env, uint32_t value)
486 ppc_tb_t *tb_env = env->tb_env;
488 cpu_ppc_store_tb(tb_env,
489 ((uint64_t)cpu_ppc_load_tbu(env) << 32) | value);
492 uint32_t cpu_ppc_load_decr (CPUState *env)
494 ppc_tb_t *tb_env = env->tb_env;
498 diff = tb_env->decr_next - qemu_get_clock(vm_clock);
500 decr = muldiv64(diff, tb_env->tb_freq, ticks_per_sec);
502 decr = -muldiv64(-diff, tb_env->tb_freq, ticks_per_sec);
503 #if defined(DEBUG_TB)
505 fprintf(logfile, "%s: 0x%08x\n", __func__, decr);
512 /* When decrementer expires,
513 * all we need to do is generate or queue a CPU exception
515 static inline void cpu_ppc_decr_excp (CPUState *env)
520 fprintf(logfile, "raise decrementer exception\n");
523 ppc_set_irq(env, PPC_INTERRUPT_DECR, 1);
526 static void _cpu_ppc_store_decr (CPUState *env, uint32_t decr,
527 uint32_t value, int is_excp)
529 ppc_tb_t *tb_env = env->tb_env;
534 fprintf(logfile, "%s: 0x%08x => 0x%08x\n", __func__, decr, value);
537 now = qemu_get_clock(vm_clock);
538 next = now + muldiv64(value, ticks_per_sec, tb_env->tb_freq);
540 next += tb_env->decr_next - now;
543 tb_env->decr_next = next;
545 qemu_mod_timer(tb_env->decr_timer, next);
546 /* If we set a negative value and the decrementer was positive,
547 * raise an exception.
549 if ((value & 0x80000000) && !(decr & 0x80000000))
550 cpu_ppc_decr_excp(env);
553 void cpu_ppc_store_decr (CPUState *env, uint32_t value)
555 _cpu_ppc_store_decr(env, cpu_ppc_load_decr(env), value, 0);
558 static void cpu_ppc_decr_cb (void *opaque)
560 _cpu_ppc_store_decr(opaque, 0x00000000, 0xFFFFFFFF, 1);
563 static void cpu_ppc_set_tb_clk (void *opaque, uint32_t freq)
565 CPUState *env = opaque;
566 ppc_tb_t *tb_env = env->tb_env;
568 tb_env->tb_freq = freq;
569 /* There is a bug in Linux 2.4 kernels:
570 * if a decrementer exception is pending when it enables msr_ee at startup,
571 * it's not ready to handle it...
573 _cpu_ppc_store_decr(env, 0xFFFFFFFF, 0xFFFFFFFF, 0);
576 /* Set up (once) timebase frequency (in Hz) */
577 clk_setup_cb cpu_ppc_tb_init (CPUState *env, uint32_t freq)
581 tb_env = qemu_mallocz(sizeof(ppc_tb_t));
584 env->tb_env = tb_env;
585 /* Create new timer */
586 tb_env->decr_timer = qemu_new_timer(vm_clock, &cpu_ppc_decr_cb, env);
587 cpu_ppc_set_tb_clk(env, freq);
589 return &cpu_ppc_set_tb_clk;
592 /* Specific helpers for POWER & PowerPC 601 RTC */
593 clk_setup_cb cpu_ppc601_rtc_init (CPUState *env)
595 return cpu_ppc_tb_init(env, 7812500);
598 void cpu_ppc601_store_rtcu (CPUState *env, uint32_t value)
599 __attribute__ (( alias ("cpu_ppc_store_tbu") ));
601 uint32_t cpu_ppc601_load_rtcu (CPUState *env)
602 __attribute__ (( alias ("cpu_ppc_load_tbu") ));
604 void cpu_ppc601_store_rtcl (CPUState *env, uint32_t value)
606 cpu_ppc_store_tbl(env, value & 0x3FFFFF80);
609 uint32_t cpu_ppc601_load_rtcl (CPUState *env)
611 return cpu_ppc_load_tbl(env) & 0x3FFFFF80;
614 /*****************************************************************************/
615 /* Embedded PowerPC timers */
618 typedef struct ppcemb_timer_t ppcemb_timer_t;
619 struct ppcemb_timer_t {
620 uint64_t pit_reload; /* PIT auto-reload value */
621 uint64_t fit_next; /* Tick for next FIT interrupt */
622 struct QEMUTimer *fit_timer;
623 uint64_t wdt_next; /* Tick for next WDT interrupt */
624 struct QEMUTimer *wdt_timer;
627 /* Fixed interval timer */
628 static void cpu_4xx_fit_cb (void *opaque)
632 ppcemb_timer_t *ppcemb_timer;
636 tb_env = env->tb_env;
637 ppcemb_timer = tb_env->opaque;
638 now = qemu_get_clock(vm_clock);
639 switch ((env->spr[SPR_40x_TCR] >> 24) & 0x3) {
653 /* Cannot occur, but makes gcc happy */
656 next = now + muldiv64(next, ticks_per_sec, tb_env->tb_freq);
659 qemu_mod_timer(ppcemb_timer->fit_timer, next);
660 tb_env->decr_next = next;
661 env->spr[SPR_40x_TSR] |= 1 << 26;
662 if ((env->spr[SPR_40x_TCR] >> 23) & 0x1)
663 ppc_set_irq(env, PPC_INTERRUPT_FIT, 1);
665 fprintf(logfile, "%s: ir %d TCR " ADDRX " TSR " ADDRX "\n", __func__,
666 (int)((env->spr[SPR_40x_TCR] >> 23) & 0x1),
667 env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]);
671 /* Programmable interval timer */
672 static void cpu_4xx_pit_cb (void *opaque)
676 ppcemb_timer_t *ppcemb_timer;
680 tb_env = env->tb_env;
681 ppcemb_timer = tb_env->opaque;
682 now = qemu_get_clock(vm_clock);
683 if ((env->spr[SPR_40x_TCR] >> 22) & 0x1) {
685 next = now + muldiv64(ppcemb_timer->pit_reload,
686 ticks_per_sec, tb_env->tb_freq);
689 qemu_mod_timer(tb_env->decr_timer, next);
690 tb_env->decr_next = next;
692 env->spr[SPR_40x_TSR] |= 1 << 27;
693 if ((env->spr[SPR_40x_TCR] >> 26) & 0x1)
694 ppc_set_irq(env, PPC_INTERRUPT_PIT, 1);
696 fprintf(logfile, "%s: ar %d ir %d TCR " ADDRX " TSR " ADDRX " "
697 "%016" PRIx64 "\n", __func__,
698 (int)((env->spr[SPR_40x_TCR] >> 22) & 0x1),
699 (int)((env->spr[SPR_40x_TCR] >> 26) & 0x1),
700 env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR],
701 ppcemb_timer->pit_reload);
706 static void cpu_4xx_wdt_cb (void *opaque)
710 ppcemb_timer_t *ppcemb_timer;
714 tb_env = env->tb_env;
715 ppcemb_timer = tb_env->opaque;
716 now = qemu_get_clock(vm_clock);
717 switch ((env->spr[SPR_40x_TCR] >> 30) & 0x3) {
731 /* Cannot occur, but makes gcc happy */
734 next = now + muldiv64(next, ticks_per_sec, tb_env->tb_freq);
738 fprintf(logfile, "%s: TCR " ADDRX " TSR " ADDRX "\n", __func__,
739 env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]);
741 switch ((env->spr[SPR_40x_TSR] >> 30) & 0x3) {
744 qemu_mod_timer(ppcemb_timer->wdt_timer, next);
745 ppcemb_timer->wdt_next = next;
746 env->spr[SPR_40x_TSR] |= 1 << 31;
749 qemu_mod_timer(ppcemb_timer->wdt_timer, next);
750 ppcemb_timer->wdt_next = next;
751 env->spr[SPR_40x_TSR] |= 1 << 30;
752 if ((env->spr[SPR_40x_TCR] >> 27) & 0x1)
753 ppc_set_irq(env, PPC_INTERRUPT_WDT, 1);
756 env->spr[SPR_40x_TSR] &= ~0x30000000;
757 env->spr[SPR_40x_TSR] |= env->spr[SPR_40x_TCR] & 0x30000000;
758 switch ((env->spr[SPR_40x_TCR] >> 28) & 0x3) {
762 case 0x1: /* Core reset */
763 ppc40x_core_reset(env);
765 case 0x2: /* Chip reset */
766 ppc40x_chip_reset(env);
768 case 0x3: /* System reset */
769 ppc40x_system_reset(env);
775 void store_40x_pit (CPUState *env, target_ulong val)
778 ppcemb_timer_t *ppcemb_timer;
781 tb_env = env->tb_env;
782 ppcemb_timer = tb_env->opaque;
784 fprintf(logfile, "%s %p %p\n", __func__, tb_env, ppcemb_timer);
786 ppcemb_timer->pit_reload = val;
790 fprintf(logfile, "%s: stop PIT\n", __func__);
792 qemu_del_timer(tb_env->decr_timer);
795 fprintf(logfile, "%s: start PIT 0x" ADDRX "\n", __func__, val);
797 now = qemu_get_clock(vm_clock);
798 next = now + muldiv64(val, ticks_per_sec, tb_env->tb_freq);
801 qemu_mod_timer(tb_env->decr_timer, next);
802 tb_env->decr_next = next;
806 target_ulong load_40x_pit (CPUState *env)
808 return cpu_ppc_load_decr(env);
811 void store_booke_tsr (CPUState *env, target_ulong val)
813 env->spr[SPR_40x_TSR] = val & 0xFC000000;
816 void store_booke_tcr (CPUState *env, target_ulong val)
818 env->spr[SPR_40x_TCR] = val & 0xFF800000;
822 clk_setup_cb ppc_emb_timers_init (CPUState *env, uint32_t freq)
825 ppcemb_timer_t *ppcemb_timer;
827 tb_env = qemu_mallocz(sizeof(ppc_tb_t));
830 env->tb_env = tb_env;
831 ppcemb_timer = qemu_mallocz(sizeof(ppcemb_timer_t));
832 tb_env->tb_freq = freq;
833 tb_env->opaque = ppcemb_timer;
835 fprintf(logfile, "%s %p %p\n", __func__, tb_env, ppcemb_timer);
837 if (ppcemb_timer != NULL) {
838 /* We use decr timer for PIT */
839 tb_env->decr_timer = qemu_new_timer(vm_clock, &cpu_4xx_pit_cb, env);
840 ppcemb_timer->fit_timer =
841 qemu_new_timer(vm_clock, &cpu_4xx_fit_cb, env);
842 ppcemb_timer->wdt_timer =
843 qemu_new_timer(vm_clock, &cpu_4xx_wdt_cb, env);
846 /* XXX: TODO: add callback for clock frequency change */
850 /*****************************************************************************/
851 /* Embedded PowerPC Device Control Registers */
852 typedef struct ppc_dcrn_t ppc_dcrn_t;
854 dcr_read_cb dcr_read;
855 dcr_write_cb dcr_write;
861 ppc_dcrn_t dcrn[DCRN_NB];
862 int (*read_error)(int dcrn);
863 int (*write_error)(int dcrn);
866 int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, target_ulong *valp)
870 if (dcrn < 0 || dcrn >= DCRN_NB)
872 dcr = &dcr_env->dcrn[dcrn];
873 if (dcr->dcr_read == NULL)
875 *valp = (*dcr->dcr_read)(dcr->opaque, dcrn);
880 if (dcr_env->read_error != NULL)
881 return (*dcr_env->read_error)(dcrn);
886 int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val)
890 if (dcrn < 0 || dcrn >= DCRN_NB)
892 dcr = &dcr_env->dcrn[dcrn];
893 if (dcr->dcr_write == NULL)
895 (*dcr->dcr_write)(dcr->opaque, dcrn, val);
900 if (dcr_env->write_error != NULL)
901 return (*dcr_env->write_error)(dcrn);
906 int ppc_dcr_register (CPUState *env, int dcrn, void *opaque,
907 dcr_read_cb dcr_read, dcr_write_cb dcr_write)
912 dcr_env = env->dcr_env;
915 if (dcrn < 0 || dcrn >= DCRN_NB)
917 dcr = &dcr_env->dcrn[dcrn];
918 if (dcr->opaque != NULL ||
919 dcr->dcr_read != NULL ||
920 dcr->dcr_write != NULL)
922 dcr->opaque = opaque;
923 dcr->dcr_read = dcr_read;
924 dcr->dcr_write = dcr_write;
929 int ppc_dcr_init (CPUState *env, int (*read_error)(int dcrn),
930 int (*write_error)(int dcrn))
934 dcr_env = qemu_mallocz(sizeof(ppc_dcr_t));
937 dcr_env->read_error = read_error;
938 dcr_env->write_error = write_error;
939 env->dcr_env = dcr_env;
946 /*****************************************************************************/
947 /* Handle system reset (for now, just stop emulation) */
948 void cpu_ppc_reset (CPUState *env)
950 printf("Reset asked... Stop emulation\n");
955 /*****************************************************************************/
957 void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val)
969 printf("Set loglevel to %04x\n", val);
970 cpu_set_log(val | 0x100);
975 /*****************************************************************************/
977 void NVRAM_set_byte (m48t59_t *nvram, uint32_t addr, uint8_t value)
979 m48t59_write(nvram, addr, value);
982 uint8_t NVRAM_get_byte (m48t59_t *nvram, uint32_t addr)
984 return m48t59_read(nvram, addr);
987 void NVRAM_set_word (m48t59_t *nvram, uint32_t addr, uint16_t value)
989 m48t59_write(nvram, addr, value >> 8);
990 m48t59_write(nvram, addr + 1, value & 0xFF);
993 uint16_t NVRAM_get_word (m48t59_t *nvram, uint32_t addr)
997 tmp = m48t59_read(nvram, addr) << 8;
998 tmp |= m48t59_read(nvram, addr + 1);
1002 void NVRAM_set_lword (m48t59_t *nvram, uint32_t addr, uint32_t value)
1004 m48t59_write(nvram, addr, value >> 24);
1005 m48t59_write(nvram, addr + 1, (value >> 16) & 0xFF);
1006 m48t59_write(nvram, addr + 2, (value >> 8) & 0xFF);
1007 m48t59_write(nvram, addr + 3, value & 0xFF);
1010 uint32_t NVRAM_get_lword (m48t59_t *nvram, uint32_t addr)
1014 tmp = m48t59_read(nvram, addr) << 24;
1015 tmp |= m48t59_read(nvram, addr + 1) << 16;
1016 tmp |= m48t59_read(nvram, addr + 2) << 8;
1017 tmp |= m48t59_read(nvram, addr + 3);
1022 void NVRAM_set_string (m48t59_t *nvram, uint32_t addr,
1023 const unsigned char *str, uint32_t max)
1027 for (i = 0; i < max && str[i] != '\0'; i++) {
1028 m48t59_write(nvram, addr + i, str[i]);
1030 m48t59_write(nvram, addr + max - 1, '\0');
1033 int NVRAM_get_string (m48t59_t *nvram, uint8_t *dst, uint16_t addr, int max)
1037 memset(dst, 0, max);
1038 for (i = 0; i < max; i++) {
1039 dst[i] = NVRAM_get_byte(nvram, addr + i);
1047 static uint16_t NVRAM_crc_update (uint16_t prev, uint16_t value)
1050 uint16_t pd, pd1, pd2;
1055 pd2 = ((pd >> 4) & 0x000F) ^ pd1;
1056 tmp ^= (pd1 << 3) | (pd1 << 8);
1057 tmp ^= pd2 | (pd2 << 7) | (pd2 << 12);
1062 uint16_t NVRAM_compute_crc (m48t59_t *nvram, uint32_t start, uint32_t count)
1065 uint16_t crc = 0xFFFF;
1070 for (i = 0; i != count; i++) {
1071 crc = NVRAM_crc_update(crc, NVRAM_get_word(nvram, start + i));
1074 crc = NVRAM_crc_update(crc, NVRAM_get_byte(nvram, start + i) << 8);
1080 #define CMDLINE_ADDR 0x017ff000
1082 int PPC_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size,
1083 const unsigned char *arch,
1084 uint32_t RAM_size, int boot_device,
1085 uint32_t kernel_image, uint32_t kernel_size,
1086 const char *cmdline,
1087 uint32_t initrd_image, uint32_t initrd_size,
1088 uint32_t NVRAM_image,
1089 int width, int height, int depth)
1093 /* Set parameters for Open Hack'Ware BIOS */
1094 NVRAM_set_string(nvram, 0x00, "QEMU_BIOS", 16);
1095 NVRAM_set_lword(nvram, 0x10, 0x00000002); /* structure v2 */
1096 NVRAM_set_word(nvram, 0x14, NVRAM_size);
1097 NVRAM_set_string(nvram, 0x20, arch, 16);
1098 NVRAM_set_lword(nvram, 0x30, RAM_size);
1099 NVRAM_set_byte(nvram, 0x34, boot_device);
1100 NVRAM_set_lword(nvram, 0x38, kernel_image);
1101 NVRAM_set_lword(nvram, 0x3C, kernel_size);
1103 /* XXX: put the cmdline in NVRAM too ? */
1104 strcpy(phys_ram_base + CMDLINE_ADDR, cmdline);
1105 NVRAM_set_lword(nvram, 0x40, CMDLINE_ADDR);
1106 NVRAM_set_lword(nvram, 0x44, strlen(cmdline));
1108 NVRAM_set_lword(nvram, 0x40, 0);
1109 NVRAM_set_lword(nvram, 0x44, 0);
1111 NVRAM_set_lword(nvram, 0x48, initrd_image);
1112 NVRAM_set_lword(nvram, 0x4C, initrd_size);
1113 NVRAM_set_lword(nvram, 0x50, NVRAM_image);
1115 NVRAM_set_word(nvram, 0x54, width);
1116 NVRAM_set_word(nvram, 0x56, height);
1117 NVRAM_set_word(nvram, 0x58, depth);
1118 crc = NVRAM_compute_crc(nvram, 0x00, 0xF8);
1119 NVRAM_set_word(nvram, 0xFC, crc);