2 * Arm PrimeCell PL181 MultiMedia Card Interface
4 * Copyright (c) 2007 CodeSourcery.
5 * Written by Paul Brook
7 * This code is licenced under the GPL.
13 //#define DEBUG_PL181 1
16 #define DPRINTF(fmt, args...) \
17 do { printf("pl181: " fmt , ##args); } while (0)
19 #define DPRINTF(fmt, args...) do {} while(0)
22 #define PL181_FIFO_LEN 16
42 uint32_t fifo[PL181_FIFO_LEN];
46 #define PL181_CMD_INDEX 0x3f
47 #define PL181_CMD_RESPONSE (1 << 6)
48 #define PL181_CMD_LONGRESP (1 << 7)
49 #define PL181_CMD_INTERRUPT (1 << 8)
50 #define PL181_CMD_PENDING (1 << 9)
51 #define PL181_CMD_ENABLE (1 << 10)
53 #define PL181_DATA_ENABLE (1 << 0)
54 #define PL181_DATA_DIRECTION (1 << 1)
55 #define PL181_DATA_MODE (1 << 2)
56 #define PL181_DATA_DMAENABLE (1 << 3)
58 #define PL181_STATUS_CMDCRCFAIL (1 << 0)
59 #define PL181_STATUS_DATACRCFAIL (1 << 1)
60 #define PL181_STATUS_CMDTIMEOUT (1 << 2)
61 #define PL181_STATUS_DATATIMEOUT (1 << 3)
62 #define PL181_STATUS_TXUNDERRUN (1 << 4)
63 #define PL181_STATUS_RXOVERRUN (1 << 5)
64 #define PL181_STATUS_CMDRESPEND (1 << 6)
65 #define PL181_STATUS_CMDSENT (1 << 7)
66 #define PL181_STATUS_DATAEND (1 << 8)
67 #define PL181_STATUS_DATABLOCKEND (1 << 10)
68 #define PL181_STATUS_CMDACTIVE (1 << 11)
69 #define PL181_STATUS_TXACTIVE (1 << 12)
70 #define PL181_STATUS_RXACTIVE (1 << 13)
71 #define PL181_STATUS_TXFIFOHALFEMPTY (1 << 14)
72 #define PL181_STATUS_RXFIFOHALFFULL (1 << 15)
73 #define PL181_STATUS_TXFIFOFULL (1 << 16)
74 #define PL181_STATUS_RXFIFOFULL (1 << 17)
75 #define PL181_STATUS_TXFIFOEMPTY (1 << 18)
76 #define PL181_STATUS_RXFIFOEMPTY (1 << 19)
77 #define PL181_STATUS_TXDATAAVLBL (1 << 20)
78 #define PL181_STATUS_RXDATAAVLBL (1 << 21)
80 #define PL181_STATUS_TX_FIFO (PL181_STATUS_TXACTIVE \
81 |PL181_STATUS_TXFIFOHALFEMPTY \
82 |PL181_STATUS_TXFIFOFULL \
83 |PL181_STATUS_TXFIFOEMPTY \
84 |PL181_STATUS_TXDATAAVLBL)
85 #define PL181_STATUS_RX_FIFO (PL181_STATUS_RXACTIVE \
86 |PL181_STATUS_RXFIFOHALFFULL \
87 |PL181_STATUS_RXFIFOFULL \
88 |PL181_STATUS_RXFIFOEMPTY \
89 |PL181_STATUS_RXDATAAVLBL)
91 static const unsigned char pl181_id[] =
92 { 0x81, 0x11, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };
94 static void pl181_update(pl181_state *s)
97 for (i = 0; i < 2; i++) {
98 qemu_set_irq(s->irq[i], (s->status & s->mask[i]) != 0);
102 static void pl181_fifo_push(pl181_state *s, uint32_t value)
106 if (s->fifo_len == PL181_FIFO_LEN) {
107 fprintf(stderr, "pl181: FIFO overflow\n");
110 n = (s->fifo_pos + s->fifo_len) & (PL181_FIFO_LEN - 1);
113 DPRINTF("FIFO push %08x\n", (int)value);
116 static uint32_t pl181_fifo_pop(pl181_state *s)
120 if (s->fifo_len == 0) {
121 fprintf(stderr, "pl181: FIFO underflow\n");
124 value = s->fifo[s->fifo_pos];
126 s->fifo_pos = (s->fifo_pos + 1) & (PL181_FIFO_LEN - 1);
127 DPRINTF("FIFO pop %08x\n", (int)value);
131 static void pl181_send_command(pl181_state *s)
133 struct sd_request_s request;
134 uint8_t response[16];
137 request.cmd = s->cmd & PL181_CMD_INDEX;
138 request.arg = s->cmdarg;
139 DPRINTF("Command %d %08x\n", request.cmd, request.arg);
140 rlen = sd_do_command(s->card, &request, response);
143 if (s->cmd & PL181_CMD_RESPONSE) {
144 #define RWORD(n) ((response[n] << 24) | (response[n + 1] << 16) \
145 | (response[n + 2] << 8) | response[n + 3])
146 if (rlen == 0 || (rlen == 4 && (s->cmd & PL181_CMD_LONGRESP)))
148 if (rlen != 4 && rlen != 16)
150 s->response[0] = RWORD(0);
152 s->response[1] = s->response[2] = s->response[3] = 0;
154 s->response[1] = RWORD(4);
155 s->response[2] = RWORD(8);
156 s->response[3] = RWORD(12) & ~1;
158 DPRINTF("Response recieved\n");
159 s->status |= PL181_STATUS_CMDRESPEND;
162 DPRINTF("Command sent\n");
163 s->status |= PL181_STATUS_CMDSENT;
168 DPRINTF("Timeout\n");
169 s->status |= PL181_STATUS_CMDTIMEOUT;
172 /* Transfer data between teh card and the FIFO. This is complicated by
173 the FIFO holding 32-bit words and the card taking data in single byte
174 chunks. FIFO bytes are transferred in little-endian order. */
176 static void pl181_fifo_run(pl181_state *s)
184 is_read = (s->datactrl & PL181_DATA_DIRECTION) != 0;
185 if (s->datacnt != 0 && (!is_read || sd_data_ready(s->card))) {
186 limit = is_read ? PL181_FIFO_LEN : 0;
189 while (s->datacnt && s->fifo_len != limit) {
191 value |= (uint32_t)sd_read_data(s->card) << (n * 8);
194 pl181_fifo_push(s, value);
200 value = pl181_fifo_pop(s);
203 sd_write_data(s->card, value & 0xff);
210 pl181_fifo_push(s, value);
213 s->status &= ~(PL181_STATUS_RX_FIFO | PL181_STATUS_TX_FIFO);
214 if (s->datacnt == 0) {
215 s->status |= PL181_STATUS_DATAEND;
217 s->status |= PL181_STATUS_DATABLOCKEND;
218 DPRINTF("Transfer Complete\n");
220 if (s->datacnt == 0 && s->fifocnt == 0) {
221 s->datactrl &= ~PL181_DATA_ENABLE;
222 DPRINTF("Data engine idle\n");
224 /* Update FIFO bits. */
225 bits = PL181_STATUS_TXACTIVE | PL181_STATUS_RXACTIVE;
226 if (s->fifo_len == 0) {
227 bits |= PL181_STATUS_TXFIFOEMPTY;
228 bits |= PL181_STATUS_RXFIFOEMPTY;
230 bits |= PL181_STATUS_TXDATAAVLBL;
231 bits |= PL181_STATUS_RXDATAAVLBL;
233 if (s->fifo_len == 16) {
234 bits |= PL181_STATUS_TXFIFOFULL;
235 bits |= PL181_STATUS_RXFIFOFULL;
237 if (s->fifo_len <= 8) {
238 bits |= PL181_STATUS_TXFIFOHALFEMPTY;
240 if (s->fifo_len >= 8) {
241 bits |= PL181_STATUS_RXFIFOHALFFULL;
243 if (s->datactrl & PL181_DATA_DIRECTION) {
244 bits &= PL181_STATUS_RX_FIFO;
246 bits &= PL181_STATUS_TX_FIFO;
252 static uint32_t pl181_read(void *opaque, target_phys_addr_t offset)
254 pl181_state *s = (pl181_state *)opaque;
257 if (offset >= 0xfe0 && offset < 0x1000) {
258 return pl181_id[(offset - 0xfe0) >> 2];
261 case 0x00: /* Power */
263 case 0x04: /* Clock */
265 case 0x08: /* Argument */
267 case 0x0c: /* Command */
269 case 0x10: /* RespCmd */
271 case 0x14: /* Response0 */
272 return s->response[0];
273 case 0x18: /* Response1 */
274 return s->response[1];
275 case 0x1c: /* Response2 */
276 return s->response[2];
277 case 0x20: /* Response3 */
278 return s->response[3];
279 case 0x24: /* DataTimer */
281 case 0x28: /* DataLength */
282 return s->datalength;
283 case 0x2c: /* DataCtrl */
285 case 0x30: /* DataCnt */
287 case 0x34: /* Status */
289 case 0x3c: /* Mask0 */
291 case 0x40: /* Mask1 */
293 case 0x48: /* FifoCnt */
295 case 0x80: case 0x84: case 0x88: case 0x8c: /* FifoData */
296 case 0x90: case 0x94: case 0x98: case 0x9c:
297 case 0xa0: case 0xa4: case 0xa8: case 0xac:
298 case 0xb0: case 0xb4: case 0xb8: case 0xbc:
299 if (s->fifocnt == 0) {
300 fprintf(stderr, "pl181: Unexpected FIFO read\n");
305 value = pl181_fifo_pop(s);
311 cpu_abort (cpu_single_env, "pl181_read: Bad offset %x\n", offset);
316 static void pl181_write(void *opaque, target_phys_addr_t offset,
319 pl181_state *s = (pl181_state *)opaque;
323 case 0x00: /* Power */
324 s->power = value & 0xff;
326 case 0x04: /* Clock */
327 s->clock = value & 0xff;
329 case 0x08: /* Argument */
332 case 0x0c: /* Command */
334 if (s->cmd & PL181_CMD_ENABLE) {
335 if (s->cmd & PL181_CMD_INTERRUPT) {
336 fprintf(stderr, "pl181: Interrupt mode not implemented\n");
338 } if (s->cmd & PL181_CMD_PENDING) {
339 fprintf(stderr, "pl181: Pending commands not implemented\n");
342 pl181_send_command(s);
345 /* The command has completed one way or the other. */
346 s->cmd &= ~PL181_CMD_ENABLE;
349 case 0x24: /* DataTimer */
350 s->datatimer = value;
352 case 0x28: /* DataLength */
353 s->datalength = value & 0xffff;
355 case 0x2c: /* DataCtrl */
356 s->datactrl = value & 0xff;
357 if (value & PL181_DATA_ENABLE) {
358 s->datacnt = s->datalength;
359 s->fifocnt = (s->datalength + 3) >> 2;
363 case 0x38: /* Clear */
364 s->status &= ~(value & 0x7ff);
366 case 0x3c: /* Mask0 */
369 case 0x40: /* Mask1 */
372 case 0x80: case 0x84: case 0x88: case 0x8c: /* FifoData */
373 case 0x90: case 0x94: case 0x98: case 0x9c:
374 case 0xa0: case 0xa4: case 0xa8: case 0xac:
375 case 0xb0: case 0xb4: case 0xb8: case 0xbc:
376 if (s->fifocnt == 0) {
377 fprintf(stderr, "pl181: Unexpected FIFO write\n");
380 pl181_fifo_push(s, value);
385 cpu_abort (cpu_single_env, "pl181_write: Bad offset %x\n", offset);
390 static CPUReadMemoryFunc *pl181_readfn[] = {
396 static CPUWriteMemoryFunc *pl181_writefn[] = {
402 static void pl181_reset(void *opaque)
404 pl181_state *s = (pl181_state *)opaque;
426 void pl181_init(uint32_t base, BlockDriverState *bd,
427 qemu_irq irq0, qemu_irq irq1)
432 s = (pl181_state *)qemu_mallocz(sizeof(pl181_state));
433 iomemtype = cpu_register_io_memory(0, pl181_readfn,
435 cpu_register_physical_memory(base, 0x00000fff, iomemtype);
437 s->card = sd_init(bd);
440 qemu_register_reset(pl181_reset, s);
442 /* ??? Save/restore. */