2 * CFI parallel flash with AMD command set emulation
4 * Copyright (c) 2005 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 * For now, this code can emulate flashes of 1, 2 or 4 bytes width.
23 * Supported commands/modes are:
29 * - unlock bypass command
32 * It does not support flash interleaving.
33 * It does not implement boot blocs with reduced size
34 * It does not implement software data protection as found in many real chips
35 * It does not implement erase suspend/resume commands
36 * It does not implement multiple sectors erase
41 //#define PFLASH_DEBUG
43 #define DPRINTF(fmt, args...) \
46 fprintf(logfile, "PFLASH: " fmt , ##args); \
48 printf("PFLASH: " fmt , ##args); \
51 #define DPRINTF(fmt, args...) do { } while (0)
57 target_ulong sector_len;
58 target_ulong total_len;
60 int wcycle; /* if 0, the flash is read normally */
67 uint8_t cfi_table[0x52];
74 static void pflash_timer (void *opaque)
76 pflash_t *pfl = opaque;
78 DPRINTF("%s: command %02x done\n", __func__, pfl->cmd);
84 cpu_register_physical_memory(pfl->base, pfl->total_len,
85 pfl->off | IO_MEM_ROMD | pfl->fl_mem);
91 static uint32_t pflash_read (pflash_t *pfl, target_ulong offset, int width)
97 DPRINTF("%s: offset %08x\n", __func__, offset);
100 boff = offset & 0xFF;
103 else if (pfl->width == 4)
107 /* This should never happen : reset state & treat it as a read*/
108 DPRINTF("%s: unknown command state: %x\n", __func__, pfl->cmd);
112 /* We accept reads during second unlock sequence... */
115 /* Flash area read */
120 // DPRINTF("%s: data offset %08x %02x\n", __func__, offset, ret);
123 #if defined(TARGET_WORDS_BIGENDIAN)
124 ret = p[offset] << 8;
125 ret |= p[offset + 1];
128 ret |= p[offset + 1] << 8;
130 // DPRINTF("%s: data offset %08x %04x\n", __func__, offset, ret);
133 #if defined(TARGET_WORDS_BIGENDIAN)
134 ret = p[offset] << 24;
135 ret |= p[offset + 1] << 16;
136 ret |= p[offset + 2] << 8;
137 ret |= p[offset + 3];
140 ret |= p[offset + 1] << 8;
141 ret |= p[offset + 1] << 8;
142 ret |= p[offset + 2] << 16;
143 ret |= p[offset + 3] << 24;
145 // DPRINTF("%s: data offset %08x %08x\n", __func__, offset, ret);
154 ret = pfl->ident[boff & 0x01];
157 ret = 0x00; /* Pretend all sectors are unprotected */
161 if (pfl->ident[2 + (boff & 0x01)] == (uint8_t)-1)
163 ret = pfl->ident[2 + (boff & 0x01)];
168 DPRINTF("%s: ID %d %x\n", __func__, boff, ret);
173 /* Status register read */
175 DPRINTF("%s: status %x\n", __func__, ret);
181 if (boff > pfl->cfi_len)
184 ret = pfl->cfi_table[boff];
191 /* update flash content on disk */
192 static void pflash_update(pflash_t *pfl, int offset,
197 offset_end = offset + size;
198 /* round to sectors */
199 offset = offset >> 9;
200 offset_end = (offset_end + 511) >> 9;
201 bdrv_write(pfl->bs, offset, pfl->storage + (offset << 9),
202 offset_end - offset);
206 static void pflash_write (pflash_t *pfl, target_ulong offset, uint32_t value,
213 /* WARNING: when the memory area is in ROMD mode, the offset is a
214 ram offset, not a physical address */
215 if (pfl->wcycle == 0)
221 DPRINTF("%s: offset %08x %08x %d\n", __func__, offset, value, width);
222 if (pfl->cmd != 0xA0 && cmd == 0xF0) {
223 DPRINTF("%s: flash reset asked (%02x %02x)\n",
224 __func__, pfl->cmd, cmd);
227 /* Set the device in I/O access mode */
228 cpu_register_physical_memory(pfl->base, pfl->total_len, pfl->fl_mem);
229 boff = offset & (pfl->sector_len - 1);
232 else if (pfl->width == 4)
234 switch (pfl->wcycle) {
236 /* We're in read mode */
238 if (boff == 0x55 && cmd == 0x98) {
240 /* Enter CFI query mode */
245 if (boff != 0x555 || cmd != 0xAA) {
246 DPRINTF("%s: unlock0 failed %04x %02x %04x\n",
247 __func__, boff, cmd, 0x555);
250 DPRINTF("%s: unlock sequence started\n", __func__);
253 /* We started an unlock sequence */
255 if (boff != 0x2AA || cmd != 0x55) {
256 DPRINTF("%s: unlock1 failed %04x %02x\n", __func__, boff, cmd);
259 DPRINTF("%s: unlock sequence done\n", __func__);
262 /* We finished an unlock sequence */
263 if (!pfl->bypass && boff != 0x555) {
264 DPRINTF("%s: command failed %04x %02x\n", __func__, boff, cmd);
275 DPRINTF("%s: starting command %02x\n", __func__, cmd);
278 DPRINTF("%s: unknown command %02x\n", __func__, cmd);
285 /* We need another unlock sequence */
288 DPRINTF("%s: write data offset %08x %08x %d\n",
289 __func__, offset, value, width);
294 pflash_update(pfl, offset, 1);
297 #if defined(TARGET_WORDS_BIGENDIAN)
298 p[offset] &= value >> 8;
299 p[offset + 1] &= value;
302 p[offset + 1] &= value >> 8;
304 pflash_update(pfl, offset, 2);
307 #if defined(TARGET_WORDS_BIGENDIAN)
308 p[offset] &= value >> 24;
309 p[offset + 1] &= value >> 16;
310 p[offset + 2] &= value >> 8;
311 p[offset + 3] &= value;
314 p[offset + 1] &= value >> 8;
315 p[offset + 2] &= value >> 16;
316 p[offset + 3] &= value >> 24;
318 pflash_update(pfl, offset, 4);
321 pfl->status = 0x00 | ~(value & 0x80);
322 /* Let's pretend write is immediate */
327 if (pfl->bypass && cmd == 0x00) {
328 /* Unlock bypass reset */
331 /* We can enter CFI query mode from autoselect mode */
332 if (boff == 0x55 && cmd == 0x98)
336 DPRINTF("%s: invalid write for command %02x\n",
343 /* Ignore writes while flash data write is occuring */
344 /* As we suppose write is immediate, this should never happen */
349 /* Should never happen */
350 DPRINTF("%s: invalid command state %02x (wc 4)\n",
359 DPRINTF("%s: chip erase: invalid address %04x\n",
364 DPRINTF("%s: start chip erase\n", __func__);
365 memset(pfl->storage, 0xFF, pfl->total_len);
367 pflash_update(pfl, 0, pfl->total_len);
368 /* Let's wait 5 seconds before chip erase is done */
369 qemu_mod_timer(pfl->timer,
370 qemu_get_clock(vm_clock) + (ticks_per_sec * 5));
375 offset &= ~(pfl->sector_len - 1);
376 DPRINTF("%s: start sector erase at %08x\n", __func__, offset);
377 memset(p + offset, 0xFF, pfl->sector_len);
378 pflash_update(pfl, offset, pfl->sector_len);
380 /* Let's wait 1/2 second before sector erase is done */
381 qemu_mod_timer(pfl->timer,
382 qemu_get_clock(vm_clock) + (ticks_per_sec / 2));
385 DPRINTF("%s: invalid command %02x (wc 5)\n", __func__, cmd);
393 /* Ignore writes during chip erase */
396 /* Ignore writes during sector erase */
399 /* Should never happen */
400 DPRINTF("%s: invalid command state %02x (wc 6)\n",
405 case 7: /* Special value for CFI queries */
406 DPRINTF("%s: invalid write in CFI query mode\n", __func__);
409 /* Should never happen */
410 DPRINTF("%s: invalid write state (wc 7)\n", __func__);
419 if (pfl->wcycle != 0) {
420 cpu_register_physical_memory(pfl->base, pfl->total_len,
421 pfl->off | IO_MEM_ROMD | pfl->fl_mem);
435 static uint32_t pflash_readb (void *opaque, target_phys_addr_t addr)
437 return pflash_read(opaque, addr, 1);
440 static uint32_t pflash_readw (void *opaque, target_phys_addr_t addr)
442 pflash_t *pfl = opaque;
444 return pflash_read(pfl, addr, 2);
447 static uint32_t pflash_readl (void *opaque, target_phys_addr_t addr)
449 pflash_t *pfl = opaque;
451 return pflash_read(pfl, addr, 4);
454 static void pflash_writeb (void *opaque, target_phys_addr_t addr,
457 pflash_write(opaque, addr, value, 1);
460 static void pflash_writew (void *opaque, target_phys_addr_t addr,
463 pflash_t *pfl = opaque;
465 pflash_write(pfl, addr, value, 2);
468 static void pflash_writel (void *opaque, target_phys_addr_t addr,
471 pflash_t *pfl = opaque;
473 pflash_write(pfl, addr, value, 4);
476 static CPUWriteMemoryFunc *pflash_write_ops[] = {
482 static CPUReadMemoryFunc *pflash_read_ops[] = {
488 /* Count trailing zeroes of a 32 bits quantity */
489 static int ctz32 (uint32_t n)
514 #if 0 /* This is not necessary as n is never 0 */
522 pflash_t *pflash_register (target_ulong base, ram_addr_t off,
523 BlockDriverState *bs,
524 target_ulong sector_len, int nb_blocs, int width,
525 uint16_t id0, uint16_t id1,
526 uint16_t id2, uint16_t id3)
529 target_long total_len;
531 total_len = sector_len * nb_blocs;
532 /* XXX: to be fixed */
533 if (total_len != (8 * 1024 * 1024) && total_len != (16 * 1024 * 1024) &&
534 total_len != (32 * 1024 * 1024) && total_len != (64 * 1024 * 1024))
536 pfl = qemu_mallocz(sizeof(pflash_t));
539 pfl->storage = phys_ram_base + off;
540 pfl->fl_mem = cpu_register_io_memory(0, pflash_read_ops, pflash_write_ops, pfl);
542 cpu_register_physical_memory(base, total_len,
543 off | pfl->fl_mem | IO_MEM_ROMD);
546 /* read the initial flash content */
547 bdrv_read(pfl->bs, 0, pfl->storage, total_len >> 9);
549 #if 0 /* XXX: there should be a bit to set up read-only,
550 * the same way the hardware does (with WP pin).
556 pfl->timer = qemu_new_timer(vm_clock, pflash_timer, pfl);
558 pfl->sector_len = sector_len;
559 pfl->total_len = total_len;
568 /* Hardcoded CFI table (mostly from SG29 Spansion flash) */
570 /* Standard "QRY" string */
571 pfl->cfi_table[0x10] = 'Q';
572 pfl->cfi_table[0x11] = 'R';
573 pfl->cfi_table[0x12] = 'Y';
574 /* Command set (AMD/Fujitsu) */
575 pfl->cfi_table[0x13] = 0x02;
576 pfl->cfi_table[0x14] = 0x00;
577 /* Primary extended table address (none) */
578 pfl->cfi_table[0x15] = 0x00;
579 pfl->cfi_table[0x16] = 0x00;
580 /* Alternate command set (none) */
581 pfl->cfi_table[0x17] = 0x00;
582 pfl->cfi_table[0x18] = 0x00;
583 /* Alternate extended table (none) */
584 pfl->cfi_table[0x19] = 0x00;
585 pfl->cfi_table[0x1A] = 0x00;
587 pfl->cfi_table[0x1B] = 0x27;
589 pfl->cfi_table[0x1C] = 0x36;
590 /* Vpp min (no Vpp pin) */
591 pfl->cfi_table[0x1D] = 0x00;
592 /* Vpp max (no Vpp pin) */
593 pfl->cfi_table[0x1E] = 0x00;
595 pfl->cfi_table[0x1F] = 0x07;
596 /* Timeout for min size buffer write (16 µs) */
597 pfl->cfi_table[0x20] = 0x04;
598 /* Typical timeout for block erase (512 ms) */
599 pfl->cfi_table[0x21] = 0x09;
600 /* Typical timeout for full chip erase (4096 ms) */
601 pfl->cfi_table[0x22] = 0x0C;
603 pfl->cfi_table[0x23] = 0x01;
604 /* Max timeout for buffer write */
605 pfl->cfi_table[0x24] = 0x04;
606 /* Max timeout for block erase */
607 pfl->cfi_table[0x25] = 0x0A;
608 /* Max timeout for chip erase */
609 pfl->cfi_table[0x26] = 0x0D;
611 pfl->cfi_table[0x27] = ctz32(total_len) + 1;
612 /* Flash device interface (8 & 16 bits) */
613 pfl->cfi_table[0x28] = 0x02;
614 pfl->cfi_table[0x29] = 0x00;
615 /* Max number of bytes in multi-bytes write */
616 pfl->cfi_table[0x2A] = 0x05;
617 pfl->cfi_table[0x2B] = 0x00;
618 /* Number of erase block regions (uniform) */
619 pfl->cfi_table[0x2C] = 0x01;
620 /* Erase block region 1 */
621 pfl->cfi_table[0x2D] = nb_blocs - 1;
622 pfl->cfi_table[0x2E] = (nb_blocs - 1) >> 8;
623 pfl->cfi_table[0x2F] = sector_len >> 8;
624 pfl->cfi_table[0x30] = sector_len >> 16;