2 * CFI parallel flash with AMD command set emulation
4 * Copyright (c) 2005 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 * For now, this code can emulate flashes of 1, 2 or 4 bytes width.
23 * Supported commands/modes are:
29 * - unlock bypass command
32 * It does not support flash interleaving.
33 * It does not implement boot blocs with reduced size
34 * It does not implement software data protection as found in many real chips
35 * It does not implement erase suspend/resume commands
36 * It does not implement multiple sectors erase
41 //#define PFLASH_DEBUG
43 #define DPRINTF(fmt, args...) \
45 printf("PFLASH: " fmt , ##args); \
48 #define DPRINTF(fmt, args...) do { } while (0)
54 target_ulong sector_len;
55 target_ulong total_len;
57 int wcycle; /* if 0, the flash is read normally */
64 uint8_t cfi_table[0x52];
71 static void pflash_timer (void *opaque)
73 pflash_t *pfl = opaque;
75 DPRINTF("%s: command %02x done\n", __func__, pfl->cmd);
81 cpu_register_physical_memory(pfl->base, pfl->total_len,
82 pfl->off | IO_MEM_ROMD | pfl->fl_mem);
88 static uint32_t pflash_read (pflash_t *pfl, target_ulong offset, int width)
94 DPRINTF("%s: offset %08x\n", __func__, offset);
100 else if (pfl->width == 4)
104 /* This should never happen : reset state & treat it as a read*/
105 DPRINTF("%s: unknown command state: %x\n", __func__, pfl->cmd);
109 /* We accept reads during second unlock sequence... */
112 /* Flash area read */
117 // DPRINTF("%s: data offset %08x %02x\n", __func__, offset, ret);
120 #if defined(TARGET_WORDS_BIGENDIAN)
121 ret = p[offset] << 8;
122 ret |= p[offset + 1];
125 ret |= p[offset + 1] << 8;
127 // DPRINTF("%s: data offset %08x %04x\n", __func__, offset, ret);
130 #if defined(TARGET_WORDS_BIGENDIAN)
131 ret = p[offset] << 24;
132 ret |= p[offset + 1] << 16;
133 ret |= p[offset + 2] << 8;
134 ret |= p[offset + 3];
137 ret |= p[offset + 1] << 8;
138 ret |= p[offset + 1] << 8;
139 ret |= p[offset + 2] << 16;
140 ret |= p[offset + 3] << 24;
142 // DPRINTF("%s: data offset %08x %08x\n", __func__, offset, ret);
151 ret = pfl->ident[boff & 0x01];
154 ret = 0x00; /* Pretend all sectors are unprotected */
158 if (pfl->ident[2 + (boff & 0x01)] == (uint8_t)-1)
160 ret = pfl->ident[2 + (boff & 0x01)];
165 DPRINTF("%s: ID %d %x\n", __func__, boff, ret);
170 /* Status register read */
172 DPRINTF("%s: status %x\n", __func__, ret);
178 if (boff > pfl->cfi_len)
181 ret = pfl->cfi_table[boff];
188 /* update flash content on disk */
189 static void pflash_update(pflash_t *pfl, int offset,
194 offset_end = offset + size;
195 /* round to sectors */
196 offset = offset >> 9;
197 offset_end = (offset_end + 511) >> 9;
198 bdrv_write(pfl->bs, offset, pfl->storage + (offset << 9),
199 offset_end - offset);
203 static void pflash_write (pflash_t *pfl, target_ulong offset, uint32_t value,
210 /* WARNING: when the memory area is in ROMD mode, the offset is a
211 ram offset, not a physical address */
212 if (pfl->wcycle == 0)
213 offset -= (target_ulong)(long)pfl->storage;
218 DPRINTF("%s: offset %08x %08x %d\n", __func__, offset, value, width);
219 if (pfl->cmd != 0xA0 && cmd == 0xF0) {
220 DPRINTF("%s: flash reset asked (%02x %02x)\n",
221 __func__, pfl->cmd, cmd);
224 /* Set the device in I/O access mode */
225 cpu_register_physical_memory(pfl->base, pfl->total_len, pfl->fl_mem);
226 boff = offset & (pfl->sector_len - 1);
229 else if (pfl->width == 4)
231 switch (pfl->wcycle) {
233 /* We're in read mode */
235 if (boff == 0x55 && cmd == 0x98) {
237 /* Enter CFI query mode */
242 if (boff != 0x555 || cmd != 0xAA) {
243 DPRINTF("%s: unlock0 failed %04x %02x %04x\n",
244 __func__, boff, cmd, 0x555);
247 DPRINTF("%s: unlock sequence started\n", __func__);
250 /* We started an unlock sequence */
252 if (boff != 0x2AA || cmd != 0x55) {
253 DPRINTF("%s: unlock1 failed %04x %02x\n", __func__, boff, cmd);
256 DPRINTF("%s: unlock sequence done\n", __func__);
259 /* We finished an unlock sequence */
260 if (!pfl->bypass && boff != 0x555) {
261 DPRINTF("%s: command failed %04x %02x\n", __func__, boff, cmd);
272 DPRINTF("%s: starting command %02x\n", __func__, cmd);
275 DPRINTF("%s: unknown command %02x\n", __func__, cmd);
282 /* We need another unlock sequence */
285 DPRINTF("%s: write data offset %08x %08x %d\n",
286 __func__, offset, value, width);
291 pflash_update(pfl, offset, 1);
294 #if defined(TARGET_WORDS_BIGENDIAN)
295 p[offset] &= value >> 8;
296 p[offset + 1] &= value;
299 p[offset + 1] &= value >> 8;
301 pflash_update(pfl, offset, 2);
304 #if defined(TARGET_WORDS_BIGENDIAN)
305 p[offset] &= value >> 24;
306 p[offset + 1] &= value >> 16;
307 p[offset + 2] &= value >> 8;
308 p[offset + 3] &= value;
311 p[offset + 1] &= value >> 8;
312 p[offset + 2] &= value >> 16;
313 p[offset + 3] &= value >> 24;
315 pflash_update(pfl, offset, 4);
318 pfl->status = 0x00 | ~(value & 0x80);
319 /* Let's pretend write is immediate */
324 if (pfl->bypass && cmd == 0x00) {
325 /* Unlock bypass reset */
328 /* We can enter CFI query mode from autoselect mode */
329 if (boff == 0x55 && cmd == 0x98)
333 DPRINTF("%s: invalid write for command %02x\n",
340 /* Ignore writes while flash data write is occuring */
341 /* As we suppose write is immediate, this should never happen */
346 /* Should never happen */
347 DPRINTF("%s: invalid command state %02x (wc 4)\n",
356 DPRINTF("%s: chip erase: invalid address %04x\n",
361 DPRINTF("%s: start chip erase\n", __func__);
362 memset(pfl->storage, 0xFF, pfl->total_len);
364 pflash_update(pfl, 0, pfl->total_len);
365 /* Let's wait 5 seconds before chip erase is done */
366 qemu_mod_timer(pfl->timer,
367 qemu_get_clock(vm_clock) + (ticks_per_sec * 5));
372 offset &= ~(pfl->sector_len - 1);
373 DPRINTF("%s: start sector erase at %08x\n", __func__, offset);
374 memset(p + offset, 0xFF, pfl->sector_len);
375 pflash_update(pfl, offset, pfl->sector_len);
377 /* Let's wait 1/2 second before sector erase is done */
378 qemu_mod_timer(pfl->timer,
379 qemu_get_clock(vm_clock) + (ticks_per_sec / 2));
382 DPRINTF("%s: invalid command %02x (wc 5)\n", __func__, cmd);
390 /* Ignore writes during chip erase */
393 /* Ignore writes during sector erase */
396 /* Should never happen */
397 DPRINTF("%s: invalid command state %02x (wc 6)\n",
402 case 7: /* Special value for CFI queries */
403 DPRINTF("%s: invalid write in CFI query mode\n", __func__);
406 /* Should never happen */
407 DPRINTF("%s: invalid write state (wc 7)\n", __func__);
416 if (pfl->wcycle != 0) {
417 cpu_register_physical_memory(pfl->base, pfl->total_len,
418 pfl->off | IO_MEM_ROMD | pfl->fl_mem);
432 static uint32_t pflash_readb (void *opaque, target_phys_addr_t addr)
434 return pflash_read(opaque, addr, 1);
437 static uint32_t pflash_readw (void *opaque, target_phys_addr_t addr)
439 pflash_t *pfl = opaque;
441 return pflash_read(pfl, addr, 2);
444 static uint32_t pflash_readl (void *opaque, target_phys_addr_t addr)
446 pflash_t *pfl = opaque;
448 return pflash_read(pfl, addr, 4);
451 static void pflash_writeb (void *opaque, target_phys_addr_t addr,
454 pflash_write(opaque, addr, value, 1);
457 static void pflash_writew (void *opaque, target_phys_addr_t addr,
460 pflash_t *pfl = opaque;
462 pflash_write(pfl, addr, value, 2);
465 static void pflash_writel (void *opaque, target_phys_addr_t addr,
468 pflash_t *pfl = opaque;
470 pflash_write(pfl, addr, value, 4);
473 static CPUWriteMemoryFunc *pflash_write_ops[] = {
479 static CPUReadMemoryFunc *pflash_read_ops[] = {
485 /* Count trailing zeroes of a 32 bits quantity */
486 static int ctz32 (uint32_t n)
511 #if 0 /* This is not necessary as n is never 0 */
519 pflash_t *pflash_register (target_ulong base, ram_addr_t off,
520 BlockDriverState *bs,
521 target_ulong sector_len, int nb_blocs, int width,
522 uint16_t id0, uint16_t id1,
523 uint16_t id2, uint16_t id3)
526 target_long total_len;
528 total_len = sector_len * nb_blocs;
529 /* XXX: to be fixed */
530 if (total_len != (8 * 1024 * 1024) && total_len != (16 * 1024 * 1024) &&
531 total_len != (32 * 1024 * 1024) && total_len != (64 * 1024 * 1024))
533 pfl = qemu_mallocz(sizeof(pflash_t));
536 pfl->storage = phys_ram_base + off;
537 pfl->fl_mem = cpu_register_io_memory(0, pflash_read_ops, pflash_write_ops, pfl);
539 cpu_register_physical_memory(base, total_len,
540 off | pfl->fl_mem | IO_MEM_ROMD);
543 /* read the initial flash content */
544 bdrv_read(pfl->bs, 0, pfl->storage, total_len >> 9);
546 #if 0 /* XXX: there should be a bit to set up read-only,
547 * the same way the hardware does (with WP pin).
553 pfl->timer = qemu_new_timer(vm_clock, pflash_timer, pfl);
555 pfl->sector_len = sector_len;
556 pfl->total_len = total_len;
565 /* Hardcoded CFI table (mostly from SG29 Spansion flash) */
567 /* Standard "QRY" string */
568 pfl->cfi_table[0x10] = 'Q';
569 pfl->cfi_table[0x11] = 'R';
570 pfl->cfi_table[0x12] = 'Y';
571 /* Command set (AMD/Fujitsu) */
572 pfl->cfi_table[0x13] = 0x02;
573 pfl->cfi_table[0x14] = 0x00;
574 /* Primary extended table address (none) */
575 pfl->cfi_table[0x15] = 0x00;
576 pfl->cfi_table[0x16] = 0x00;
577 /* Alternate command set (none) */
578 pfl->cfi_table[0x17] = 0x00;
579 pfl->cfi_table[0x18] = 0x00;
580 /* Alternate extended table (none) */
581 pfl->cfi_table[0x19] = 0x00;
582 pfl->cfi_table[0x1A] = 0x00;
584 pfl->cfi_table[0x1B] = 0x27;
586 pfl->cfi_table[0x1C] = 0x36;
587 /* Vpp min (no Vpp pin) */
588 pfl->cfi_table[0x1D] = 0x00;
589 /* Vpp max (no Vpp pin) */
590 pfl->cfi_table[0x1E] = 0x00;
592 pfl->cfi_table[0x1F] = 0x07;
593 /* Timeout for min size buffer write (16 µs) */
594 pfl->cfi_table[0x20] = 0x04;
595 /* Typical timeout for block erase (512 ms) */
596 pfl->cfi_table[0x21] = 0x09;
597 /* Typical timeout for full chip erase (4096 ms) */
598 pfl->cfi_table[0x22] = 0x0C;
600 pfl->cfi_table[0x23] = 0x01;
601 /* Max timeout for buffer write */
602 pfl->cfi_table[0x24] = 0x04;
603 /* Max timeout for block erase */
604 pfl->cfi_table[0x25] = 0x0A;
605 /* Max timeout for chip erase */
606 pfl->cfi_table[0x26] = 0x0D;
608 pfl->cfi_table[0x27] = ctz32(total_len) + 1;
609 /* Flash device interface (8 & 16 bits) */
610 pfl->cfi_table[0x28] = 0x02;
611 pfl->cfi_table[0x29] = 0x00;
612 /* Max number of bytes in multi-bytes write */
613 pfl->cfi_table[0x2A] = 0x05;
614 pfl->cfi_table[0x2B] = 0x00;
615 /* Number of erase block regions (uniform) */
616 pfl->cfi_table[0x2C] = 0x01;
617 /* Erase block region 1 */
618 pfl->cfi_table[0x2D] = nb_blocs - 1;
619 pfl->cfi_table[0x2E] = (nb_blocs - 1) >> 8;
620 pfl->cfi_table[0x2F] = sector_len >> 8;
621 pfl->cfi_table[0x30] = sector_len >> 16;