2 * QEMU Parallel PORT emulation
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 * Copyright (c) 2007 Marko Kohtala
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 #include "qemu-char.h"
30 //#define DEBUG_PARALLEL
33 #define pdebug(fmt, arg...) printf("pp: " fmt, ##arg)
35 #define pdebug(fmt, arg...) ((void)0)
38 #define PARA_REG_DATA 0
39 #define PARA_REG_STS 1
40 #define PARA_REG_CTR 2
41 #define PARA_REG_EPP_ADDR 3
42 #define PARA_REG_EPP_DATA 4
45 * These are the definitions for the Printer Status Register
47 #define PARA_STS_BUSY 0x80 /* Busy complement */
48 #define PARA_STS_ACK 0x40 /* Acknowledge */
49 #define PARA_STS_PAPER 0x20 /* Out of paper */
50 #define PARA_STS_ONLINE 0x10 /* Online */
51 #define PARA_STS_ERROR 0x08 /* Error complement */
52 #define PARA_STS_TMOUT 0x01 /* EPP timeout */
55 * These are the definitions for the Printer Control Register
57 #define PARA_CTR_DIR 0x20 /* Direction (1=read, 0=write) */
58 #define PARA_CTR_INTEN 0x10 /* IRQ Enable */
59 #define PARA_CTR_SELECT 0x08 /* Select In complement */
60 #define PARA_CTR_INIT 0x04 /* Initialize Printer complement */
61 #define PARA_CTR_AUTOLF 0x02 /* Auto linefeed complement */
62 #define PARA_CTR_STROBE 0x01 /* Strobe complement */
64 #define PARA_CTR_SIGNAL (PARA_CTR_SELECT|PARA_CTR_INIT|PARA_CTR_AUTOLF|PARA_CTR_STROBE)
66 struct ParallelState {
76 uint32_t last_read_offset; /* For debugging */
77 /* Memory-mapped interface */
78 target_phys_addr_t base;
82 static void parallel_update_irq(ParallelState *s)
85 qemu_irq_raise(s->irq);
87 qemu_irq_lower(s->irq);
91 parallel_ioport_write_sw(void *opaque, uint32_t addr, uint32_t val)
93 ParallelState *s = opaque;
95 pdebug("write addr=0x%02x val=0x%02x\n", addr, val);
101 parallel_update_irq(s);
105 if ((val & PARA_CTR_INIT) == 0 ) {
106 s->status = PARA_STS_BUSY;
107 s->status |= PARA_STS_ACK;
108 s->status |= PARA_STS_ONLINE;
109 s->status |= PARA_STS_ERROR;
111 else if (val & PARA_CTR_SELECT) {
112 if (val & PARA_CTR_STROBE) {
113 s->status &= ~PARA_STS_BUSY;
114 if ((s->control & PARA_CTR_STROBE) == 0)
115 qemu_chr_write(s->chr, &s->dataw, 1);
117 if (s->control & PARA_CTR_INTEN) {
122 parallel_update_irq(s);
128 static void parallel_ioport_write_hw(void *opaque, uint32_t addr, uint32_t val)
130 ParallelState *s = opaque;
133 /* Sometimes programs do several writes for timing purposes on old
134 HW. Take care not to waste time on writes that do nothing. */
136 s->last_read_offset = ~0U;
143 pdebug("wd%02x\n", val);
144 qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_WRITE_DATA, &parm);
148 pdebug("ws%02x\n", val);
149 if (val & PARA_STS_TMOUT)
154 if (s->control == val)
156 pdebug("wc%02x\n", val);
157 qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_WRITE_CONTROL, &parm);
160 case PARA_REG_EPP_ADDR:
161 if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT)
162 /* Controls not correct for EPP address cycle, so do nothing */
163 pdebug("wa%02x s\n", val);
165 struct ParallelIOArg ioarg = { .buffer = &parm, .count = 1 };
166 if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE_ADDR, &ioarg)) {
168 pdebug("wa%02x t\n", val);
171 pdebug("wa%02x\n", val);
174 case PARA_REG_EPP_DATA:
175 if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT)
176 /* Controls not correct for EPP data cycle, so do nothing */
177 pdebug("we%02x s\n", val);
179 struct ParallelIOArg ioarg = { .buffer = &parm, .count = 1 };
180 if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg)) {
182 pdebug("we%02x t\n", val);
185 pdebug("we%02x\n", val);
192 parallel_ioport_eppdata_write_hw2(void *opaque, uint32_t addr, uint32_t val)
194 ParallelState *s = opaque;
195 uint16_t eppdata = cpu_to_le16(val);
197 struct ParallelIOArg ioarg = {
198 .buffer = &eppdata, .count = sizeof(eppdata)
200 if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT) {
201 /* Controls not correct for EPP data cycle, so do nothing */
202 pdebug("we%04x s\n", val);
205 err = qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg);
208 pdebug("we%04x t\n", val);
211 pdebug("we%04x\n", val);
215 parallel_ioport_eppdata_write_hw4(void *opaque, uint32_t addr, uint32_t val)
217 ParallelState *s = opaque;
218 uint32_t eppdata = cpu_to_le32(val);
220 struct ParallelIOArg ioarg = {
221 .buffer = &eppdata, .count = sizeof(eppdata)
223 if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT) {
224 /* Controls not correct for EPP data cycle, so do nothing */
225 pdebug("we%08x s\n", val);
228 err = qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg);
231 pdebug("we%08x t\n", val);
234 pdebug("we%08x\n", val);
237 static uint32_t parallel_ioport_read_sw(void *opaque, uint32_t addr)
239 ParallelState *s = opaque;
245 if (s->control & PARA_CTR_DIR)
253 if ((s->status & PARA_STS_BUSY) == 0 && (s->control & PARA_CTR_STROBE) == 0) {
254 /* XXX Fixme: wait 5 microseconds */
255 if (s->status & PARA_STS_ACK)
256 s->status &= ~PARA_STS_ACK;
258 /* XXX Fixme: wait 5 microseconds */
259 s->status |= PARA_STS_ACK;
260 s->status |= PARA_STS_BUSY;
263 parallel_update_irq(s);
269 pdebug("read addr=0x%02x val=0x%02x\n", addr, ret);
273 static uint32_t parallel_ioport_read_hw(void *opaque, uint32_t addr)
275 ParallelState *s = opaque;
280 qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_READ_DATA, &ret);
281 if (s->last_read_offset != addr || s->datar != ret)
282 pdebug("rd%02x\n", ret);
286 qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_READ_STATUS, &ret);
287 ret &= ~PARA_STS_TMOUT;
289 ret |= PARA_STS_TMOUT;
290 if (s->last_read_offset != addr || s->status != ret)
291 pdebug("rs%02x\n", ret);
295 /* s->control has some bits fixed to 1. It is zero only when
296 it has not been yet written to. */
297 if (s->control == 0) {
298 qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_READ_CONTROL, &ret);
299 if (s->last_read_offset != addr)
300 pdebug("rc%02x\n", ret);
305 if (s->last_read_offset != addr)
306 pdebug("rc%02x\n", ret);
309 case PARA_REG_EPP_ADDR:
310 if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT))
311 /* Controls not correct for EPP addr cycle, so do nothing */
312 pdebug("ra%02x s\n", ret);
314 struct ParallelIOArg ioarg = { .buffer = &ret, .count = 1 };
315 if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ_ADDR, &ioarg)) {
317 pdebug("ra%02x t\n", ret);
320 pdebug("ra%02x\n", ret);
323 case PARA_REG_EPP_DATA:
324 if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT))
325 /* Controls not correct for EPP data cycle, so do nothing */
326 pdebug("re%02x s\n", ret);
328 struct ParallelIOArg ioarg = { .buffer = &ret, .count = 1 };
329 if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg)) {
331 pdebug("re%02x t\n", ret);
334 pdebug("re%02x\n", ret);
338 s->last_read_offset = addr;
343 parallel_ioport_eppdata_read_hw2(void *opaque, uint32_t addr)
345 ParallelState *s = opaque;
347 uint16_t eppdata = ~0;
349 struct ParallelIOArg ioarg = {
350 .buffer = &eppdata, .count = sizeof(eppdata)
352 if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT)) {
353 /* Controls not correct for EPP data cycle, so do nothing */
354 pdebug("re%04x s\n", eppdata);
357 err = qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg);
358 ret = le16_to_cpu(eppdata);
362 pdebug("re%04x t\n", ret);
365 pdebug("re%04x\n", ret);
370 parallel_ioport_eppdata_read_hw4(void *opaque, uint32_t addr)
372 ParallelState *s = opaque;
374 uint32_t eppdata = ~0U;
376 struct ParallelIOArg ioarg = {
377 .buffer = &eppdata, .count = sizeof(eppdata)
379 if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT)) {
380 /* Controls not correct for EPP data cycle, so do nothing */
381 pdebug("re%08x s\n", eppdata);
384 err = qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg);
385 ret = le32_to_cpu(eppdata);
389 pdebug("re%08x t\n", ret);
392 pdebug("re%08x\n", ret);
396 static void parallel_ioport_ecp_write(void *opaque, uint32_t addr, uint32_t val)
399 pdebug("wecp%d=%02x\n", addr, val);
402 static uint32_t parallel_ioport_ecp_read(void *opaque, uint32_t addr)
406 pdebug("recp%d:%02x\n", addr, ret);
410 static void parallel_reset(ParallelState *s, qemu_irq irq, CharDriverState *chr)
414 s->status = PARA_STS_BUSY;
415 s->status |= PARA_STS_ACK;
416 s->status |= PARA_STS_ONLINE;
417 s->status |= PARA_STS_ERROR;
418 s->status |= PARA_STS_TMOUT;
419 s->control = PARA_CTR_SELECT;
420 s->control |= PARA_CTR_INIT;
427 s->last_read_offset = ~0U;
430 /* If fd is zero, it means that the parallel device uses the console */
431 ParallelState *parallel_init(int base, qemu_irq irq, CharDriverState *chr)
436 s = qemu_mallocz(sizeof(ParallelState));
439 parallel_reset(s, irq, chr);
441 if (qemu_chr_ioctl(chr, CHR_IOCTL_PP_READ_STATUS, &dummy) == 0) {
447 register_ioport_write(base, 8, 1, parallel_ioport_write_hw, s);
448 register_ioport_read(base, 8, 1, parallel_ioport_read_hw, s);
449 register_ioport_write(base+4, 1, 2, parallel_ioport_eppdata_write_hw2, s);
450 register_ioport_read(base+4, 1, 2, parallel_ioport_eppdata_read_hw2, s);
451 register_ioport_write(base+4, 1, 4, parallel_ioport_eppdata_write_hw4, s);
452 register_ioport_read(base+4, 1, 4, parallel_ioport_eppdata_read_hw4, s);
453 register_ioport_write(base+0x400, 8, 1, parallel_ioport_ecp_write, s);
454 register_ioport_read(base+0x400, 8, 1, parallel_ioport_ecp_read, s);
457 register_ioport_write(base, 8, 1, parallel_ioport_write_sw, s);
458 register_ioport_read(base, 8, 1, parallel_ioport_read_sw, s);
463 /* Memory mapped interface */
464 static uint32_t parallel_mm_readb (void *opaque, target_phys_addr_t addr)
466 ParallelState *s = opaque;
468 return parallel_ioport_read_sw(s, (addr - s->base) >> s->it_shift) & 0xFF;
471 static void parallel_mm_writeb (void *opaque,
472 target_phys_addr_t addr, uint32_t value)
474 ParallelState *s = opaque;
476 parallel_ioport_write_sw(s, (addr - s->base) >> s->it_shift, value & 0xFF);
479 static uint32_t parallel_mm_readw (void *opaque, target_phys_addr_t addr)
481 ParallelState *s = opaque;
483 return parallel_ioport_read_sw(s, (addr - s->base) >> s->it_shift) & 0xFFFF;
486 static void parallel_mm_writew (void *opaque,
487 target_phys_addr_t addr, uint32_t value)
489 ParallelState *s = opaque;
491 parallel_ioport_write_sw(s, (addr - s->base) >> s->it_shift, value & 0xFFFF);
494 static uint32_t parallel_mm_readl (void *opaque, target_phys_addr_t addr)
496 ParallelState *s = opaque;
498 return parallel_ioport_read_sw(s, (addr - s->base) >> s->it_shift);
501 static void parallel_mm_writel (void *opaque,
502 target_phys_addr_t addr, uint32_t value)
504 ParallelState *s = opaque;
506 parallel_ioport_write_sw(s, (addr - s->base) >> s->it_shift, value);
509 static CPUReadMemoryFunc *parallel_mm_read_sw[] = {
515 static CPUWriteMemoryFunc *parallel_mm_write_sw[] = {
521 /* If fd is zero, it means that the parallel device uses the console */
522 ParallelState *parallel_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq, CharDriverState *chr)
527 s = qemu_mallocz(sizeof(ParallelState));
530 parallel_reset(s, irq, chr);
532 s->it_shift = it_shift;
534 io_sw = cpu_register_io_memory(0, parallel_mm_read_sw, parallel_mm_write_sw, s);
535 cpu_register_physical_memory(base, 8 << it_shift, io_sw);