4 * Copyright (c) 2004 Jocelyn Mayer
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 * Based on OpenPic implementations:
27 * - Intel GW80314 I/O compagnion chip developper's manual
28 * - Motorola MPC8245 & MPC8540 user manuals.
29 * - Motorola MCP750 (aka Raven) programmer manual.
30 * - Motorola Harrier programmer manuel
32 * Serial interrupts, as implemented in Raven chipset are not supported yet.
37 //#define DEBUG_OPENPIC
40 #define DPRINTF(fmt, args...) do { printf(fmt , ##args); } while (0)
42 #define DPRINTF(fmt, args...) do { } while (0)
44 #define ERROR(fmr, args...) do { printf("ERROR: " fmr , ##args); } while (0)
46 #define USE_MPCxxx /* Intel model is broken, for now */
48 #if defined (USE_INTEL_GW80314)
49 /* Intel GW80314 I/O Companion chip */
59 #define VID (0x00000000)
61 #define OPENPIC_LITTLE_ENDIAN 1
62 #define OPENPIC_BIG_ENDIAN 0
64 #elif defined(USE_MPCxxx)
74 #define VID 0x03 /* MPIC version ID */
75 #define VENI 0x00000000 /* Vendor ID */
82 #define OPENPIC_LITTLE_ENDIAN 1
83 #define OPENPIC_BIG_ENDIAN 0
86 #error "Please select which OpenPic implementation is to be emulated"
89 #if (OPENPIC_BIG_ENDIAN && !TARGET_WORDS_BIGENDIAN) || \
90 (OPENPIC_LITTLE_ENDIAN && TARGET_WORDS_BIGENDIAN)
94 /* Interrupt definitions */
95 #define IRQ_FE (EXT_IRQ) /* Internal functional IRQ */
96 #define IRQ_ERR (EXT_IRQ + 1) /* Error IRQ */
97 #define IRQ_TIM0 (EXT_IRQ + 2) /* First timer IRQ */
99 #define IRQ_IPI0 (IRQ_TIM0 + MAX_TMR) /* First IPI IRQ */
100 #define IRQ_DBL0 (IRQ_IPI0 + (MAX_CPU * MAX_IPI)) /* First doorbell IRQ */
102 #define IRQ_DBL0 (IRQ_TIM0 + MAX_TMR) /* First doorbell IRQ */
103 #define IRQ_MBX0 (IRQ_DBL0 + MAX_DBL) /* First mailbox IRQ */
106 #define BF_WIDTH(_bits_) \
107 (((_bits_) + (sizeof(uint32_t) * 8) - 1) / (sizeof(uint32_t) * 8))
109 static inline void set_bit (uint32_t *field, int bit)
111 field[bit >> 5] |= 1 << (bit & 0x1F);
114 static inline void reset_bit (uint32_t *field, int bit)
116 field[bit >> 5] &= ~(1 << (bit & 0x1F));
119 static inline int test_bit (uint32_t *field, int bit)
121 return (field[bit >> 5] & 1 << (bit & 0x1F)) != 0;
131 typedef struct IRQ_queue_t {
132 uint32_t queue[BF_WIDTH(MAX_IRQ)];
137 typedef struct IRQ_src_t {
138 uint32_t ipvp; /* IRQ vector/priority register */
139 uint32_t ide; /* IRQ destination register */
142 int pending; /* TRUE if IRQ is pending */
152 #define IPVP_PRIORITY_MASK (0x1F << 16)
153 #define IPVP_PRIORITY(_ipvpr_) ((int)(((_ipvpr_) & IPVP_PRIORITY_MASK) >> 16))
154 #define IPVP_VECTOR_MASK ((1 << VECTOR_BITS) - 1)
155 #define IPVP_VECTOR(_ipvpr_) ((_ipvpr_) & IPVP_VECTOR_MASK)
157 typedef struct IRQ_dst_t {
158 uint32_t pctp; /* CPU current task priority */
159 uint32_t pcsr; /* CPU sensitivity register */
161 IRQ_queue_t servicing;
165 typedef struct openpic_t {
168 /* Global registers */
169 uint32_t frep; /* Feature reporting register */
170 uint32_t glbc; /* Global configuration register */
171 uint32_t micr; /* MPIC interrupt configuration register */
172 uint32_t veni; /* Vendor identification register */
173 uint32_t pint; /* Processor initialization register */
174 uint32_t spve; /* Spurious vector register */
175 uint32_t tifr; /* Timer frequency reporting register */
176 /* Source registers */
177 IRQ_src_t src[MAX_IRQ];
178 /* Local registers per output pin */
179 IRQ_dst_t dst[MAX_CPU];
181 /* Timer registers */
183 uint32_t ticc; /* Global timer current count register */
184 uint32_t tibc; /* Global timer base count register */
187 /* Doorbell registers */
188 uint32_t dar; /* Doorbell activate register */
190 uint32_t dmr; /* Doorbell messaging register */
191 } doorbells[MAX_DBL];
194 /* Mailbox registers */
196 uint32_t mbr; /* Mailbox register */
197 } mailboxes[MAX_MAILBOXES];
199 /* IRQ out is used when in bypass mode (not implemented) */
203 static inline void IRQ_setbit (IRQ_queue_t *q, int n_IRQ)
205 set_bit(q->queue, n_IRQ);
208 static inline void IRQ_resetbit (IRQ_queue_t *q, int n_IRQ)
210 reset_bit(q->queue, n_IRQ);
213 static inline int IRQ_testbit (IRQ_queue_t *q, int n_IRQ)
215 return test_bit(q->queue, n_IRQ);
218 static void IRQ_check (openpic_t *opp, IRQ_queue_t *q)
225 for (i = 0; i < MAX_IRQ; i++) {
226 if (IRQ_testbit(q, i)) {
227 DPRINTF("IRQ_check: irq %d set ipvp_pr=%d pr=%d\n",
228 i, IPVP_PRIORITY(opp->src[i].ipvp), priority);
229 if (IPVP_PRIORITY(opp->src[i].ipvp) > priority) {
231 priority = IPVP_PRIORITY(opp->src[i].ipvp);
236 q->priority = priority;
239 static int IRQ_get_next (openpic_t *opp, IRQ_queue_t *q)
249 static void IRQ_local_pipe (openpic_t *opp, int n_CPU, int n_IRQ)
255 dst = &opp->dst[n_CPU];
256 src = &opp->src[n_IRQ];
257 priority = IPVP_PRIORITY(src->ipvp);
258 if (priority <= dst->pctp) {
259 /* Too low priority */
260 DPRINTF("%s: IRQ %d has too low priority on CPU %d\n",
261 __func__, n_IRQ, n_CPU);
264 if (IRQ_testbit(&dst->raised, n_IRQ)) {
266 DPRINTF("%s: IRQ %d was missed on CPU %d\n",
267 __func__, n_IRQ, n_CPU);
270 set_bit(&src->ipvp, IPVP_ACTIVITY);
271 IRQ_setbit(&dst->raised, n_IRQ);
272 if (priority < dst->raised.priority) {
273 /* An higher priority IRQ is already raised */
274 DPRINTF("%s: IRQ %d is hidden by raised IRQ %d on CPU %d\n",
275 __func__, n_IRQ, dst->raised.next, n_CPU);
278 IRQ_get_next(opp, &dst->raised);
279 if (IRQ_get_next(opp, &dst->servicing) != -1 &&
280 priority < dst->servicing.priority) {
281 DPRINTF("%s: IRQ %d is hidden by servicing IRQ %d on CPU %d\n",
282 __func__, n_IRQ, dst->servicing.next, n_CPU);
283 /* Already servicing a higher priority IRQ */
286 DPRINTF("Raise OpenPIC INT output cpu %d irq %d\n", n_CPU, n_IRQ);
287 qemu_irq_raise(dst->irqs[OPENPIC_OUTPUT_INT]);
290 /* update pic state because registers for n_IRQ have changed value */
291 static void openpic_update_irq(openpic_t *opp, int n_IRQ)
296 src = &opp->src[n_IRQ];
300 DPRINTF("%s: IRQ %d is not pending\n", __func__, n_IRQ);
303 if (test_bit(&src->ipvp, IPVP_MASK)) {
304 /* Interrupt source is disabled */
305 DPRINTF("%s: IRQ %d is disabled\n", __func__, n_IRQ);
308 if (IPVP_PRIORITY(src->ipvp) == 0) {
309 /* Priority set to zero */
310 DPRINTF("%s: IRQ %d has 0 priority\n", __func__, n_IRQ);
313 if (test_bit(&src->ipvp, IPVP_ACTIVITY)) {
314 /* IRQ already active */
315 DPRINTF("%s: IRQ %d is already active\n", __func__, n_IRQ);
318 if (src->ide == 0x00000000) {
320 DPRINTF("%s: IRQ %d has no target\n", __func__, n_IRQ);
324 if (src->ide == (1 << src->last_cpu)) {
325 /* Only one CPU is allowed to receive this IRQ */
326 IRQ_local_pipe(opp, src->last_cpu, n_IRQ);
327 } else if (!test_bit(&src->ipvp, IPVP_MODE)) {
328 /* Directed delivery mode */
329 for (i = 0; i < opp->nb_cpus; i++) {
330 if (test_bit(&src->ide, i))
331 IRQ_local_pipe(opp, i, n_IRQ);
334 /* Distributed delivery mode */
335 for (i = src->last_cpu + 1; i != src->last_cpu; i++) {
336 if (i == opp->nb_cpus)
338 if (test_bit(&src->ide, i)) {
339 IRQ_local_pipe(opp, i, n_IRQ);
347 static void openpic_set_irq(void *opaque, int n_IRQ, int level)
349 openpic_t *opp = opaque;
352 src = &opp->src[n_IRQ];
353 DPRINTF("openpic: set irq %d = %d ipvp=%08x\n",
354 n_IRQ, level, src->ipvp);
355 if (test_bit(&src->ipvp, IPVP_SENSE)) {
356 /* level-sensitive irq */
357 src->pending = level;
359 reset_bit(&src->ipvp, IPVP_ACTIVITY);
361 /* edge-sensitive irq */
365 openpic_update_irq(opp, n_IRQ);
368 static void openpic_reset (openpic_t *opp)
372 opp->glbc = 0x80000000;
373 /* Initialise controller registers */
374 opp->frep = ((EXT_IRQ - 1) << 16) | ((MAX_CPU - 1) << 8) | VID;
376 opp->pint = 0x00000000;
377 opp->spve = 0x000000FF;
378 opp->tifr = 0x003F7A00;
380 opp->micr = 0x00000000;
381 /* Initialise IRQ sources */
382 for (i = 0; i < MAX_IRQ; i++) {
383 opp->src[i].ipvp = 0xA0000000;
384 opp->src[i].ide = 0x00000000;
386 /* Initialise IRQ destinations */
387 for (i = 0; i < MAX_CPU; i++) {
388 opp->dst[i].pctp = 0x0000000F;
389 opp->dst[i].pcsr = 0x00000000;
390 memset(&opp->dst[i].raised, 0, sizeof(IRQ_queue_t));
391 memset(&opp->dst[i].servicing, 0, sizeof(IRQ_queue_t));
393 /* Initialise timers */
394 for (i = 0; i < MAX_TMR; i++) {
395 opp->timers[i].ticc = 0x00000000;
396 opp->timers[i].tibc = 0x80000000;
398 /* Initialise doorbells */
400 opp->dar = 0x00000000;
401 for (i = 0; i < MAX_DBL; i++) {
402 opp->doorbells[i].dmr = 0x00000000;
405 /* Initialise mailboxes */
407 for (i = 0; i < MAX_MBX; i++) { /* ? */
408 opp->mailboxes[i].mbr = 0x00000000;
411 /* Go out of RESET state */
412 opp->glbc = 0x00000000;
415 static inline uint32_t read_IRQreg (openpic_t *opp, int n_IRQ, uint32_t reg)
421 retval = opp->src[n_IRQ].ipvp;
424 retval = opp->src[n_IRQ].ide;
431 static inline void write_IRQreg (openpic_t *opp, int n_IRQ,
432 uint32_t reg, uint32_t val)
438 /* NOTE: not fully accurate for special IRQs, but simple and
440 /* ACTIVITY bit is read-only */
441 opp->src[n_IRQ].ipvp =
442 (opp->src[n_IRQ].ipvp & 0x40000000) |
444 openpic_update_irq(opp, n_IRQ);
445 DPRINTF("Set IPVP %d to 0x%08x -> 0x%08x\n",
446 n_IRQ, val, opp->src[n_IRQ].ipvp);
449 tmp = val & 0xC0000000;
450 tmp |= val & ((1 << MAX_CPU) - 1);
451 opp->src[n_IRQ].ide = tmp;
452 DPRINTF("Set IDE %d to 0x%08x\n", n_IRQ, opp->src[n_IRQ].ide);
457 #if 0 // Code provision for Intel model
459 static uint32_t read_doorbell_register (openpic_t *opp,
460 int n_dbl, uint32_t offset)
465 case DBL_IPVP_OFFSET:
466 retval = read_IRQreg(opp, IRQ_DBL0 + n_dbl, IRQ_IPVP);
469 retval = read_IRQreg(opp, IRQ_DBL0 + n_dbl, IRQ_IDE);
472 retval = opp->doorbells[n_dbl].dmr;
479 static void write_doorbell_register (penpic_t *opp, int n_dbl,
480 uint32_t offset, uint32_t value)
483 case DBL_IVPR_OFFSET:
484 write_IRQreg(opp, IRQ_DBL0 + n_dbl, IRQ_IPVP, value);
487 write_IRQreg(opp, IRQ_DBL0 + n_dbl, IRQ_IDE, value);
490 opp->doorbells[n_dbl].dmr = value;
497 static uint32_t read_mailbox_register (openpic_t *opp,
498 int n_mbx, uint32_t offset)
504 retval = opp->mailboxes[n_mbx].mbr;
506 case MBX_IVPR_OFFSET:
507 retval = read_IRQreg(opp, IRQ_MBX0 + n_mbx, IRQ_IPVP);
510 retval = read_IRQreg(opp, IRQ_MBX0 + n_mbx, IRQ_IDE);
517 static void write_mailbox_register (openpic_t *opp, int n_mbx,
518 uint32_t address, uint32_t value)
522 opp->mailboxes[n_mbx].mbr = value;
524 case MBX_IVPR_OFFSET:
525 write_IRQreg(opp, IRQ_MBX0 + n_mbx, IRQ_IPVP, value);
528 write_IRQreg(opp, IRQ_MBX0 + n_mbx, IRQ_IDE, value);
533 #endif /* 0 : Code provision for Intel model */
535 static void openpic_gbl_write (void *opaque, uint32_t addr, uint32_t val)
537 openpic_t *opp = opaque;
541 DPRINTF("%s: addr %08x <= %08x\n", __func__, addr, val);
544 #if defined OPENPIC_SWAP
549 case 0x00: /* FREP */
551 case 0x20: /* GLBC */
552 if (val & 0x80000000)
554 opp->glbc = val & ~0x80000000;
556 case 0x80: /* VENI */
558 case 0x90: /* PINT */
559 for (idx = 0; idx < opp->nb_cpus; idx++) {
560 if ((val & (1 << idx)) && !(opp->pint & (1 << idx))) {
561 DPRINTF("Raise OpenPIC RESET output for CPU %d\n", idx);
562 dst = &opp->dst[idx];
563 qemu_irq_raise(dst->irqs[OPENPIC_OUTPUT_RESET]);
564 } else if (!(val & (1 << idx)) && (opp->pint & (1 << idx))) {
565 DPRINTF("Lower OpenPIC RESET output for CPU %d\n", idx);
566 dst = &opp->dst[idx];
567 qemu_irq_lower(dst->irqs[OPENPIC_OUTPUT_RESET]);
573 case 0xA0: /* IPI_IPVP */
579 idx = (addr - 0xA0) >> 4;
580 write_IRQreg(opp, IRQ_IPI0 + idx, IRQ_IPVP, val);
584 case 0xE0: /* SPVE */
585 opp->spve = val & 0x000000FF;
587 case 0xF0: /* TIFR */
595 static uint32_t openpic_gbl_read (void *opaque, uint32_t addr)
597 openpic_t *opp = opaque;
600 DPRINTF("%s: addr %08x\n", __func__, addr);
606 case 0x00: /* FREP */
609 case 0x20: /* GLBC */
612 case 0x80: /* VENI */
615 case 0x90: /* PINT */
619 case 0xA0: /* IPI_IPVP */
625 idx = (addr - 0xA0) >> 4;
626 retval = read_IRQreg(opp, IRQ_IPI0 + idx, IRQ_IPVP);
630 case 0xE0: /* SPVE */
633 case 0xF0: /* TIFR */
639 DPRINTF("%s: => %08x\n", __func__, retval);
640 #if defined OPENPIC_SWAP
641 retval = bswap32(retval);
647 static void openpic_timer_write (void *opaque, uint32_t addr, uint32_t val)
649 openpic_t *opp = opaque;
652 DPRINTF("%s: addr %08x <= %08x\n", __func__, addr, val);
655 #if defined OPENPIC_SWAP
660 idx = (addr & 0xFFF0) >> 6;
663 case 0x00: /* TICC */
665 case 0x10: /* TIBC */
666 if ((opp->timers[idx].ticc & 0x80000000) != 0 &&
667 (val & 0x80000000) == 0 &&
668 (opp->timers[idx].tibc & 0x80000000) != 0)
669 opp->timers[idx].ticc &= ~0x80000000;
670 opp->timers[idx].tibc = val;
672 case 0x20: /* TIVP */
673 write_IRQreg(opp, IRQ_TIM0 + idx, IRQ_IPVP, val);
675 case 0x30: /* TIDE */
676 write_IRQreg(opp, IRQ_TIM0 + idx, IRQ_IDE, val);
681 static uint32_t openpic_timer_read (void *opaque, uint32_t addr)
683 openpic_t *opp = opaque;
687 DPRINTF("%s: addr %08x\n", __func__, addr);
693 idx = (addr & 0xFFF0) >> 6;
696 case 0x00: /* TICC */
697 retval = opp->timers[idx].ticc;
699 case 0x10: /* TIBC */
700 retval = opp->timers[idx].tibc;
702 case 0x20: /* TIPV */
703 retval = read_IRQreg(opp, IRQ_TIM0 + idx, IRQ_IPVP);
705 case 0x30: /* TIDE */
706 retval = read_IRQreg(opp, IRQ_TIM0 + idx, IRQ_IDE);
709 DPRINTF("%s: => %08x\n", __func__, retval);
710 #if defined OPENPIC_SWAP
711 retval = bswap32(retval);
717 static void openpic_src_write (void *opaque, uint32_t addr, uint32_t val)
719 openpic_t *opp = opaque;
722 DPRINTF("%s: addr %08x <= %08x\n", __func__, addr, val);
725 #if defined OPENPIC_SWAP
728 addr = addr & 0xFFF0;
731 /* EXDE / IFEDE / IEEDE */
732 write_IRQreg(opp, idx, IRQ_IDE, val);
734 /* EXVP / IFEVP / IEEVP */
735 write_IRQreg(opp, idx, IRQ_IPVP, val);
739 static uint32_t openpic_src_read (void *opaque, uint32_t addr)
741 openpic_t *opp = opaque;
745 DPRINTF("%s: addr %08x\n", __func__, addr);
749 addr = addr & 0xFFF0;
752 /* EXDE / IFEDE / IEEDE */
753 retval = read_IRQreg(opp, idx, IRQ_IDE);
755 /* EXVP / IFEVP / IEEVP */
756 retval = read_IRQreg(opp, idx, IRQ_IPVP);
758 DPRINTF("%s: => %08x\n", __func__, retval);
759 #if defined OPENPIC_SWAP
760 retval = tswap32(retval);
766 static void openpic_cpu_write (void *opaque, uint32_t addr, uint32_t val)
768 openpic_t *opp = opaque;
771 int idx, s_IRQ, n_IRQ;
773 DPRINTF("%s: addr %08x <= %08x\n", __func__, addr, val);
776 #if defined OPENPIC_SWAP
781 dst = &opp->dst[idx];
785 case 0x40: /* PIPD */
789 idx = (addr - 0x40) >> 4;
790 write_IRQreg(opp, IRQ_IPI0 + idx, IRQ_IDE, val);
791 openpic_set_irq(opp, IRQ_IPI0 + idx, 1);
792 openpic_set_irq(opp, IRQ_IPI0 + idx, 0);
795 case 0x80: /* PCTP */
796 dst->pctp = val & 0x0000000F;
798 case 0x90: /* WHOAMI */
799 /* Read-only register */
801 case 0xA0: /* PIAC */
802 /* Read-only register */
804 case 0xB0: /* PEOI */
806 s_IRQ = IRQ_get_next(opp, &dst->servicing);
807 IRQ_resetbit(&dst->servicing, s_IRQ);
808 dst->servicing.next = -1;
809 /* Set up next servicing IRQ */
810 s_IRQ = IRQ_get_next(opp, &dst->servicing);
811 /* Check queued interrupts. */
812 n_IRQ = IRQ_get_next(opp, &dst->raised);
813 src = &opp->src[n_IRQ];
816 IPVP_PRIORITY(src->ipvp) > dst->servicing.priority)) {
817 DPRINTF("Raise OpenPIC INT output cpu %d irq %d\n",
819 qemu_irq_raise(dst->irqs[OPENPIC_OUTPUT_INT]);
827 static uint32_t openpic_cpu_read (void *opaque, uint32_t addr)
829 openpic_t *opp = opaque;
835 DPRINTF("%s: addr %08x\n", __func__, addr);
841 dst = &opp->dst[idx];
844 case 0x80: /* PCTP */
847 case 0x90: /* WHOAMI */
850 case 0xA0: /* PIAC */
851 DPRINTF("Lower OpenPIC INT output\n");
852 qemu_irq_lower(dst->irqs[OPENPIC_OUTPUT_INT]);
853 n_IRQ = IRQ_get_next(opp, &dst->raised);
854 DPRINTF("PIAC: irq=%d\n", n_IRQ);
856 /* No more interrupt pending */
857 retval = IPVP_VECTOR(opp->spve);
859 src = &opp->src[n_IRQ];
860 if (!test_bit(&src->ipvp, IPVP_ACTIVITY) ||
861 !(IPVP_PRIORITY(src->ipvp) > dst->pctp)) {
862 /* - Spurious level-sensitive IRQ
863 * - Priorities has been changed
864 * and the pending IRQ isn't allowed anymore
866 reset_bit(&src->ipvp, IPVP_ACTIVITY);
867 retval = IPVP_VECTOR(opp->spve);
869 /* IRQ enter servicing state */
870 IRQ_setbit(&dst->servicing, n_IRQ);
871 retval = IPVP_VECTOR(src->ipvp);
873 IRQ_resetbit(&dst->raised, n_IRQ);
874 dst->raised.next = -1;
875 if (!test_bit(&src->ipvp, IPVP_SENSE)) {
876 /* edge-sensitive IRQ */
877 reset_bit(&src->ipvp, IPVP_ACTIVITY);
882 case 0xB0: /* PEOI */
888 idx = (addr - 0x40) >> 4;
889 retval = read_IRQreg(opp, IRQ_IPI0 + idx, IRQ_IDE);
895 DPRINTF("%s: => %08x\n", __func__, retval);
896 #if defined OPENPIC_SWAP
897 retval= bswap32(retval);
903 static void openpic_buggy_write (void *opaque,
904 target_phys_addr_t addr, uint32_t val)
906 printf("Invalid OPENPIC write access !\n");
909 static uint32_t openpic_buggy_read (void *opaque, target_phys_addr_t addr)
911 printf("Invalid OPENPIC read access !\n");
916 static void openpic_writel (void *opaque,
917 target_phys_addr_t addr, uint32_t val)
919 openpic_t *opp = opaque;
922 DPRINTF("%s: offset %08x val: %08x\n", __func__, (int)addr, val);
924 /* Global registers */
925 openpic_gbl_write(opp, addr, val);
926 } else if (addr < 0x10000) {
927 /* Timers registers */
928 openpic_timer_write(opp, addr, val);
929 } else if (addr < 0x20000) {
930 /* Source registers */
931 openpic_src_write(opp, addr, val);
934 openpic_cpu_write(opp, addr, val);
938 static uint32_t openpic_readl (void *opaque,target_phys_addr_t addr)
940 openpic_t *opp = opaque;
944 DPRINTF("%s: offset %08x\n", __func__, (int)addr);
946 /* Global registers */
947 retval = openpic_gbl_read(opp, addr);
948 } else if (addr < 0x10000) {
949 /* Timers registers */
950 retval = openpic_timer_read(opp, addr);
951 } else if (addr < 0x20000) {
952 /* Source registers */
953 retval = openpic_src_read(opp, addr);
956 retval = openpic_cpu_read(opp, addr);
962 static CPUWriteMemoryFunc *openpic_write[] = {
963 &openpic_buggy_write,
964 &openpic_buggy_write,
968 static CPUReadMemoryFunc *openpic_read[] = {
974 static void openpic_map(PCIDevice *pci_dev, int region_num,
975 uint32_t addr, uint32_t size, int type)
979 DPRINTF("Map OpenPIC\n");
980 opp = (openpic_t *)pci_dev;
981 /* Global registers */
982 DPRINTF("Register OPENPIC gbl %08x => %08x\n",
983 addr + 0x1000, addr + 0x1000 + 0x100);
984 /* Timer registers */
985 DPRINTF("Register OPENPIC timer %08x => %08x\n",
986 addr + 0x1100, addr + 0x1100 + 0x40 * MAX_TMR);
987 /* Interrupt source registers */
988 DPRINTF("Register OPENPIC src %08x => %08x\n",
989 addr + 0x10000, addr + 0x10000 + 0x20 * (EXT_IRQ + 2));
990 /* Per CPU registers */
991 DPRINTF("Register OPENPIC dst %08x => %08x\n",
992 addr + 0x20000, addr + 0x20000 + 0x1000 * MAX_CPU);
993 cpu_register_physical_memory(addr, 0x40000, opp->mem_index);
994 #if 0 // Don't implement ISU for now
995 opp_io_memory = cpu_register_io_memory(0, openpic_src_read,
997 cpu_register_physical_memory(isu_base, 0x20 * (EXT_IRQ + 2),
1002 qemu_irq *openpic_init (PCIBus *bus, int *pmem_index, int nb_cpus,
1003 qemu_irq **irqs, qemu_irq irq_out)
1009 /* XXX: for now, only one CPU is supported */
1013 opp = (openpic_t *)pci_register_device(bus, "OpenPIC", sizeof(openpic_t),
1017 pci_conf = opp->pci_dev.config;
1018 pci_conf[0x00] = 0x14; // IBM MPIC2
1019 pci_conf[0x01] = 0x10;
1020 pci_conf[0x02] = 0xFF;
1021 pci_conf[0x03] = 0xFF;
1022 pci_conf[0x0a] = 0x80; // PIC
1023 pci_conf[0x0b] = 0x08;
1024 pci_conf[0x0e] = 0x00; // header_type
1025 pci_conf[0x3d] = 0x00; // no interrupt pin
1027 /* Register I/O spaces */
1028 pci_register_io_region((PCIDevice *)opp, 0, 0x40000,
1029 PCI_ADDRESS_SPACE_MEM, &openpic_map);
1031 opp = qemu_mallocz(sizeof(openpic_t));
1033 opp->mem_index = cpu_register_io_memory(0, openpic_read,
1034 openpic_write, opp);
1036 // isu_base &= 0xFFFC0000;
1037 opp->nb_cpus = nb_cpus;
1039 for (i = 0; i < EXT_IRQ; i++) {
1040 opp->src[i].type = IRQ_EXTERNAL;
1042 for (; i < IRQ_TIM0; i++) {
1043 opp->src[i].type = IRQ_SPECIAL;
1050 for (; i < m; i++) {
1051 opp->src[i].type = IRQ_TIMER;
1053 for (; i < MAX_IRQ; i++) {
1054 opp->src[i].type = IRQ_INTERNAL;
1056 for (i = 0; i < nb_cpus; i++)
1057 opp->dst[i].irqs = irqs[i];
1058 opp->irq_out = irq_out;
1061 *pmem_index = opp->mem_index;
1063 return qemu_allocate_irqs(openpic_set_irq, opp, MAX_IRQ);