2 * OMAP on-chip MMC/SD host emulation.
4 * Copyright (C) 2006-2007 Andrzej Zaborowski <balrog@zabor.org>
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 target_phys_addr_t base;
45 uint16_t blen_counter;
47 uint16_t nblk_counter;
57 static void omap_mmc_interrupts_update(struct omap_mmc_s *s)
59 qemu_set_irq(s->irq, !!(s->status & s->mask));
62 static void omap_mmc_fifolevel_update(struct omap_mmc_s *host)
64 if (!host->transfer && !host->fifo_len) {
65 host->status &= 0xf3ff;
69 if (host->fifo_len > host->af_level && host->ddir) {
71 host->status &= 0xfbff;
72 qemu_irq_raise(host->dma[1]);
74 host->status |= 0x0400;
76 host->status &= 0xfbff;
77 qemu_irq_lower(host->dma[1]);
80 if (host->fifo_len < host->ae_level && !host->ddir) {
82 host->status &= 0xf7ff;
83 qemu_irq_raise(host->dma[0]);
85 host->status |= 0x0800;
87 qemu_irq_lower(host->dma[0]);
88 host->status &= 0xf7ff;
93 sd_nore = 0, /* no response */
94 sd_r1, /* normal response command */
95 sd_r2, /* CID, CSD registers */
96 sd_r3, /* OCR register */
97 sd_r6 = 6, /* Published RCA response */
101 static void omap_mmc_command(struct omap_mmc_s *host, int cmd, int dir,
102 sd_cmd_type_t type, int busy, sd_rsp_type_t resptype, int init)
104 uint32_t rspstatus, mask;
106 struct sd_request_s request;
107 uint8_t response[16];
109 if (resptype == sd_r1 && busy)
112 if (type == sd_adtc) {
113 host->fifo_start = 0;
124 request.arg = host->arg;
125 request.crc = 0; /* FIXME */
127 rsplen = sd_do_command(host->card, &request, response);
129 /* TODO: validate CRCs */
143 mask = OUT_OF_RANGE | ADDRESS_ERROR | BLOCK_LEN_ERROR |
144 ERASE_SEQ_ERROR | ERASE_PARAM | WP_VIOLATION |
145 LOCK_UNLOCK_FAILED | COM_CRC_ERROR | ILLEGAL_COMMAND |
146 CARD_ECC_FAILED | CC_ERROR | SD_ERROR |
148 if (host->sdio & (1 << 13))
149 mask |= AKE_SEQ_ERROR;
150 rspstatus = (response[0] << 24) | (response[1] << 16) |
151 (response[2] << 8) | (response[3] << 0);
169 rspstatus = (response[0] << 24) | (response[1] << 16) |
170 (response[2] << 8) | (response[3] << 0);
171 if (rspstatus & 0x80000000)
172 host->status &= 0xe000;
174 host->status |= 0x1000;
184 mask = 0xe000 | AKE_SEQ_ERROR;
185 rspstatus = (response[2] << 8) | (response[3] << 0);
188 if (rspstatus & mask)
189 host->status |= 0x4000;
191 host->status &= 0xb000;
194 for (rsplen = 0; rsplen < 8; rsplen ++)
195 host->rsp[~rsplen & 7] = response[(rsplen << 1) | 1] |
196 (response[(rsplen << 1) | 0] << 8);
199 host->status |= 0x0080;
201 host->status |= 0x0005; /* Makes it more real */
203 host->status |= 0x0001;
206 static void omap_mmc_transfer(struct omap_mmc_s *host)
215 if (host->fifo_len > host->af_level)
218 value = sd_read_data(host->card);
219 host->fifo[(host->fifo_start + host->fifo_len) & 31] = value;
220 if (-- host->blen_counter) {
221 value = sd_read_data(host->card);
222 host->fifo[(host->fifo_start + host->fifo_len) & 31] |=
224 host->blen_counter --;
232 value = host->fifo[host->fifo_start] & 0xff;
233 sd_write_data(host->card, value);
234 if (-- host->blen_counter) {
235 value = host->fifo[host->fifo_start] >> 8;
236 sd_write_data(host->card, value);
237 host->blen_counter --;
242 host->fifo_start &= 31;
245 if (host->blen_counter == 0) {
246 host->nblk_counter --;
247 host->blen_counter = host->blen;
249 if (host->nblk_counter == 0) {
250 host->nblk_counter = host->nblk;
252 host->status |= 0x0008;
259 static void omap_mmc_update(void *opaque)
261 struct omap_mmc_s *s = opaque;
262 omap_mmc_transfer(s);
263 omap_mmc_fifolevel_update(s);
264 omap_mmc_interrupts_update(s);
267 static uint32_t omap_mmc_read(void *opaque, target_phys_addr_t offset)
270 struct omap_mmc_s *s = (struct omap_mmc_s *) opaque;
274 case 0x00: /* MMC_CMD */
277 case 0x04: /* MMC_ARGL */
278 return s->arg & 0x0000ffff;
280 case 0x08: /* MMC_ARGH */
283 case 0x0c: /* MMC_CON */
284 return (s->dw << 15) | (s->mode << 12) | (s->enable << 11);
286 case 0x10: /* MMC_STAT */
289 case 0x14: /* MMC_IE */
292 case 0x18: /* MMC_CTO */
295 case 0x1c: /* MMC_DTO */
298 case 0x20: /* MMC_DATA */
299 /* TODO: support 8-bit access */
300 i = s->fifo[s->fifo_start];
301 if (s->fifo_len == 0) {
302 printf("MMC: FIFO underrun\n");
308 omap_mmc_transfer(s);
309 omap_mmc_fifolevel_update(s);
310 omap_mmc_interrupts_update(s);
313 case 0x24: /* MMC_BLEN */
314 return s->blen_counter;
316 case 0x28: /* MMC_NBLK */
317 return s->nblk_counter;
319 case 0x2c: /* MMC_BUF */
320 return (s->rx_dma << 15) | (s->af_level << 8) |
321 (s->tx_dma << 7) | s->ae_level;
323 case 0x30: /* MMC_SPI */
325 case 0x34: /* MMC_SDIO */
327 case 0x38: /* MMC_SYST */
330 case 0x3c: /* MMC_REV */
333 case 0x40: /* MMC_RSP0 */
334 case 0x44: /* MMC_RSP1 */
335 case 0x48: /* MMC_RSP2 */
336 case 0x4c: /* MMC_RSP3 */
337 case 0x50: /* MMC_RSP4 */
338 case 0x54: /* MMC_RSP5 */
339 case 0x58: /* MMC_RSP6 */
340 case 0x5c: /* MMC_RSP7 */
341 return s->rsp[(offset - 0x40) >> 2];
344 OMAP_BAD_REG(offset);
348 static void omap_mmc_write(void *opaque, target_phys_addr_t offset,
352 struct omap_mmc_s *s = (struct omap_mmc_s *) opaque;
356 case 0x00: /* MMC_CMD */
361 for (i = 0; i < 8; i ++)
363 omap_mmc_command(s, value & 63, (value >> 15) & 1,
364 (sd_cmd_type_t) ((value >> 12) & 3),
366 (sd_rsp_type_t) ((value >> 8) & 7),
371 case 0x04: /* MMC_ARGL */
372 s->arg &= 0xffff0000;
373 s->arg |= 0x0000ffff & value;
376 case 0x08: /* MMC_ARGH */
377 s->arg &= 0x0000ffff;
378 s->arg |= value << 16;
381 case 0x0c: /* MMC_CON */
382 s->dw = (value >> 15) & 1;
383 s->mode = (value >> 12) & 3;
384 s->enable = (value >> 11) & 1;
386 printf("SD mode %i unimplemented!\n", s->mode);
388 printf("4-bit SD bus enabled\n");
391 case 0x10: /* MMC_STAT */
393 omap_mmc_interrupts_update(s);
396 case 0x14: /* MMC_IE */
398 omap_mmc_interrupts_update(s);
401 case 0x18: /* MMC_CTO */
402 s->cto = value & 0xff;
404 printf("MMC: CTO of 0xff and 0xfe cannot be used!\n");
407 case 0x1c: /* MMC_DTO */
408 s->dto = value & 0xffff;
411 case 0x20: /* MMC_DATA */
412 /* TODO: support 8-bit access */
413 if (s->fifo_len == 32)
415 s->fifo[(s->fifo_start + s->fifo_len) & 31] = value;
417 omap_mmc_transfer(s);
418 omap_mmc_fifolevel_update(s);
419 omap_mmc_interrupts_update(s);
422 case 0x24: /* MMC_BLEN */
423 s->blen = (value & 0x07ff) + 1;
424 s->blen_counter = s->blen;
427 case 0x28: /* MMC_NBLK */
428 s->nblk = (value & 0x07ff) + 1;
429 s->nblk_counter = s->nblk;
430 s->blen_counter = s->blen;
433 case 0x2c: /* MMC_BUF */
434 s->rx_dma = (value >> 15) & 1;
435 s->af_level = (value >> 8) & 0x1f;
436 s->tx_dma = (value >> 7) & 1;
437 s->ae_level = value & 0x1f;
443 omap_mmc_fifolevel_update(s);
444 omap_mmc_interrupts_update(s);
447 /* SPI, SDIO and TEST modes unimplemented */
448 case 0x30: /* MMC_SPI */
450 case 0x34: /* MMC_SDIO */
451 s->sdio = value & 0x2020;
453 case 0x38: /* MMC_SYST */
456 case 0x3c: /* MMC_REV */
457 case 0x40: /* MMC_RSP0 */
458 case 0x44: /* MMC_RSP1 */
459 case 0x48: /* MMC_RSP2 */
460 case 0x4c: /* MMC_RSP3 */
461 case 0x50: /* MMC_RSP4 */
462 case 0x54: /* MMC_RSP5 */
463 case 0x58: /* MMC_RSP6 */
464 case 0x5c: /* MMC_RSP7 */
469 OMAP_BAD_REG(offset);
473 static CPUReadMemoryFunc *omap_mmc_readfn[] = {
474 omap_badwidth_read16,
476 omap_badwidth_read16,
479 static CPUWriteMemoryFunc *omap_mmc_writefn[] = {
480 omap_badwidth_write16,
482 omap_badwidth_write16,
485 void omap_mmc_reset(struct omap_mmc_s *host)
488 memset(host->rsp, 0, sizeof(host->rsp));
499 host->blen_counter = 0;
501 host->nblk_counter = 0;
504 host->ae_level = 0x00;
505 host->af_level = 0x1f;
509 struct omap_mmc_s *omap_mmc_init(target_phys_addr_t base,
510 qemu_irq irq, qemu_irq dma[], omap_clk clk)
513 struct omap_mmc_s *s = (struct omap_mmc_s *)
514 qemu_mallocz(sizeof(struct omap_mmc_s));
521 iomemtype = cpu_register_io_memory(0, omap_mmc_readfn,
522 omap_mmc_writefn, s);
523 cpu_register_physical_memory(s->base, 0x800, iomemtype);
525 /* Instantiate the storage */
526 s->card = sd_init(sd_bdrv);
531 /* TODO: insertion and read-only handlers */