2 * QEMU NE2000 emulation
4 * Copyright (c) 2003-2004 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 /* debug NE2000 card */
27 //#define DEBUG_NE2000
29 #define MAX_ETH_FRAME_SIZE 1514
31 #define E8390_CMD 0x00 /* The command register (for all pages) */
32 /* Page 0 register offsets. */
33 #define EN0_CLDALO 0x01 /* Low byte of current local dma addr RD */
34 #define EN0_STARTPG 0x01 /* Starting page of ring bfr WR */
35 #define EN0_CLDAHI 0x02 /* High byte of current local dma addr RD */
36 #define EN0_STOPPG 0x02 /* Ending page +1 of ring bfr WR */
37 #define EN0_BOUNDARY 0x03 /* Boundary page of ring bfr RD WR */
38 #define EN0_TSR 0x04 /* Transmit status reg RD */
39 #define EN0_TPSR 0x04 /* Transmit starting page WR */
40 #define EN0_NCR 0x05 /* Number of collision reg RD */
41 #define EN0_TCNTLO 0x05 /* Low byte of tx byte count WR */
42 #define EN0_FIFO 0x06 /* FIFO RD */
43 #define EN0_TCNTHI 0x06 /* High byte of tx byte count WR */
44 #define EN0_ISR 0x07 /* Interrupt status reg RD WR */
45 #define EN0_CRDALO 0x08 /* low byte of current remote dma address RD */
46 #define EN0_RSARLO 0x08 /* Remote start address reg 0 */
47 #define EN0_CRDAHI 0x09 /* high byte, current remote dma address RD */
48 #define EN0_RSARHI 0x09 /* Remote start address reg 1 */
49 #define EN0_RCNTLO 0x0a /* Remote byte count reg WR */
50 #define EN0_RCNTHI 0x0b /* Remote byte count reg WR */
51 #define EN0_RSR 0x0c /* rx status reg RD */
52 #define EN0_RXCR 0x0c /* RX configuration reg WR */
53 #define EN0_TXCR 0x0d /* TX configuration reg WR */
54 #define EN0_COUNTER0 0x0d /* Rcv alignment error counter RD */
55 #define EN0_DCFG 0x0e /* Data configuration reg WR */
56 #define EN0_COUNTER1 0x0e /* Rcv CRC error counter RD */
57 #define EN0_IMR 0x0f /* Interrupt mask reg WR */
58 #define EN0_COUNTER2 0x0f /* Rcv missed frame error counter RD */
61 #define EN1_CURPAG 0x17
64 /* Register accessed at EN_CMD, the 8390 base addr. */
65 #define E8390_STOP 0x01 /* Stop and reset the chip */
66 #define E8390_START 0x02 /* Start the chip, clear reset */
67 #define E8390_TRANS 0x04 /* Transmit a frame */
68 #define E8390_RREAD 0x08 /* Remote read */
69 #define E8390_RWRITE 0x10 /* Remote write */
70 #define E8390_NODMA 0x20 /* Remote DMA */
71 #define E8390_PAGE0 0x00 /* Select page chip registers */
72 #define E8390_PAGE1 0x40 /* using the two high-order bits */
73 #define E8390_PAGE2 0x80 /* Page 3 is invalid. */
75 /* Bits in EN0_ISR - Interrupt status register */
76 #define ENISR_RX 0x01 /* Receiver, no error */
77 #define ENISR_TX 0x02 /* Transmitter, no error */
78 #define ENISR_RX_ERR 0x04 /* Receiver, with error */
79 #define ENISR_TX_ERR 0x08 /* Transmitter, with error */
80 #define ENISR_OVER 0x10 /* Receiver overwrote the ring */
81 #define ENISR_COUNTERS 0x20 /* Counters need emptying */
82 #define ENISR_RDC 0x40 /* remote dma complete */
83 #define ENISR_RESET 0x80 /* Reset completed */
84 #define ENISR_ALL 0x3f /* Interrupts we will enable */
86 /* Bits in received packet status byte and EN0_RSR*/
87 #define ENRSR_RXOK 0x01 /* Received a good packet */
88 #define ENRSR_CRC 0x02 /* CRC error */
89 #define ENRSR_FAE 0x04 /* frame alignment error */
90 #define ENRSR_FO 0x08 /* FIFO overrun */
91 #define ENRSR_MPA 0x10 /* missed pkt */
92 #define ENRSR_PHY 0x20 /* physical/multicast address */
93 #define ENRSR_DIS 0x40 /* receiver disable. set in monitor mode */
94 #define ENRSR_DEF 0x80 /* deferring */
96 /* Transmitted packet status, EN0_TSR. */
97 #define ENTSR_PTX 0x01 /* Packet transmitted without error */
98 #define ENTSR_ND 0x02 /* The transmit wasn't deferred. */
99 #define ENTSR_COL 0x04 /* The transmit collided at least once. */
100 #define ENTSR_ABT 0x08 /* The transmit collided 16 times, and was deferred. */
101 #define ENTSR_CRS 0x10 /* The carrier sense was lost. */
102 #define ENTSR_FU 0x20 /* A "FIFO underrun" occurred during transmit. */
103 #define ENTSR_CDH 0x40 /* The collision detect "heartbeat" signal was lost. */
104 #define ENTSR_OWC 0x80 /* There was an out-of-window collision. */
106 #define NE2000_MEM_SIZE 32768
108 typedef struct NE2000State {
121 uint8_t phys[6]; /* mac address */
123 uint8_t mult[8]; /* multicast mask array */
126 uint8_t mem[NE2000_MEM_SIZE];
129 static void ne2000_reset(NE2000State *s)
133 s->isr = ENISR_RESET;
134 memcpy(s->mem, s->nd->macaddr, 6);
138 /* duplicate prom data */
139 for(i = 15;i >= 0; i--) {
140 s->mem[2 * i] = s->mem[i];
141 s->mem[2 * i + 1] = s->mem[i];
145 static void ne2000_update_irq(NE2000State *s)
148 isr = s->isr & s->imr;
150 pic_set_irq(s->irq, 1);
152 pic_set_irq(s->irq, 0);
155 /* return the max buffer size if the NE2000 can receive more data */
156 static int ne2000_can_receive(void *opaque)
158 NE2000State *s = opaque;
159 int avail, index, boundary;
161 if (s->cmd & E8390_STOP)
163 index = s->curpag << 8;
164 boundary = s->boundary << 8;
165 if (index < boundary)
166 avail = boundary - index;
168 avail = (s->stop - s->start) - (index - boundary);
169 if (avail < (MAX_ETH_FRAME_SIZE + 4))
171 return MAX_ETH_FRAME_SIZE;
174 #define MIN_BUF_SIZE 60
176 static void ne2000_receive(void *opaque, const uint8_t *buf, int size)
178 NE2000State *s = opaque;
180 int total_len, next, avail, len, index;
183 #if defined(DEBUG_NE2000)
184 printf("NE2000: received len=%d\n", size);
187 /* if too small buffer, then expand it */
188 if (size < MIN_BUF_SIZE) {
189 memcpy(buf1, buf, size);
190 memset(buf1 + size, 0, MIN_BUF_SIZE - size);
195 index = s->curpag << 8;
196 /* 4 bytes for header */
197 total_len = size + 4;
198 /* address for next packet (4 bytes for CRC) */
199 next = index + ((total_len + 4 + 255) & ~0xff);
201 next -= (s->stop - s->start);
202 /* prepare packet header */
204 p[0] = ENRSR_RXOK; /* receive status */
207 p[3] = total_len >> 8;
210 /* write packet data */
212 avail = s->stop - index;
216 memcpy(s->mem + index, buf, len);
219 if (index == s->stop)
223 s->curpag = next >> 8;
225 /* now we can signal we have receive something */
227 ne2000_update_irq(s);
230 static void ne2000_ioport_write(void *opaque, uint32_t addr, uint32_t val)
232 NE2000State *s = opaque;
237 printf("NE2000: write addr=0x%x val=0x%02x\n", addr, val);
239 if (addr == E8390_CMD) {
240 /* control register */
242 if (val & E8390_START) {
243 /* test specific case: zero length transfert */
244 if ((val & (E8390_RREAD | E8390_RWRITE)) &&
247 ne2000_update_irq(s);
249 if (val & E8390_TRANS) {
250 net_send_packet(s->nd, s->mem + (s->tpsr << 8), s->tcnt);
251 /* signal end of transfert */
254 ne2000_update_irq(s);
259 offset = addr | (page << 4);
272 ne2000_update_irq(s);
278 s->tcnt = (s->tcnt & 0xff00) | val;
281 s->tcnt = (s->tcnt & 0x00ff) | (val << 8);
284 s->rsar = (s->rsar & 0xff00) | val;
287 s->rsar = (s->rsar & 0x00ff) | (val << 8);
290 s->rcnt = (s->rcnt & 0xff00) | val;
293 s->rcnt = (s->rcnt & 0x00ff) | (val << 8);
300 ne2000_update_irq(s);
302 case EN1_PHYS ... EN1_PHYS + 5:
303 s->phys[offset - EN1_PHYS] = val;
308 case EN1_MULT ... EN1_MULT + 7:
309 s->mult[offset - EN1_MULT] = val;
315 static uint32_t ne2000_ioport_read(void *opaque, uint32_t addr)
317 NE2000State *s = opaque;
318 int offset, page, ret;
321 if (addr == E8390_CMD) {
325 offset = addr | (page << 4);
336 case EN1_PHYS ... EN1_PHYS + 5:
337 ret = s->phys[offset - EN1_PHYS];
342 case EN1_MULT ... EN1_MULT + 7:
343 ret = s->mult[offset - EN1_MULT];
351 printf("NE2000: read addr=0x%x val=%02x\n", addr, ret);
356 static void ne2000_asic_ioport_write(void *opaque, uint32_t addr, uint32_t val)
358 NE2000State *s = opaque;
362 printf("NE2000: asic write val=0x%04x\n", val);
364 p = s->mem + s->rsar;
365 if (s->dcfg & 0x01) {
378 if (s->rsar == s->stop)
381 /* signal end of transfert */
383 ne2000_update_irq(s);
387 static uint32_t ne2000_asic_ioport_read(void *opaque, uint32_t addr)
389 NE2000State *s = opaque;
393 p = s->mem + s->rsar;
394 if (s->dcfg & 0x01) {
396 ret = p[0] | (p[1] << 8);
406 if (s->rsar == s->stop)
409 /* signal end of transfert */
411 ne2000_update_irq(s);
414 printf("NE2000: asic read val=0x%04x\n", ret);
419 static void ne2000_reset_ioport_write(void *opaque, uint32_t addr, uint32_t val)
421 /* nothing to do (end of reset pulse) */
424 static uint32_t ne2000_reset_ioport_read(void *opaque, uint32_t addr)
426 NE2000State *s = opaque;
431 void ne2000_init(int base, int irq, NetDriverState *nd)
435 s = qemu_mallocz(sizeof(NE2000State));
439 register_ioport_write(base, 16, 1, ne2000_ioport_write, s);
440 register_ioport_read(base, 16, 1, ne2000_ioport_read, s);
442 register_ioport_write(base + 0x10, 1, 1, ne2000_asic_ioport_write, s);
443 register_ioport_read(base + 0x10, 1, 1, ne2000_asic_ioport_read, s);
444 register_ioport_write(base + 0x10, 2, 2, ne2000_asic_ioport_write, s);
445 register_ioport_read(base + 0x10, 2, 2, ne2000_asic_ioport_read, s);
447 register_ioport_write(base + 0x1f, 1, 1, ne2000_reset_ioport_write, s);
448 register_ioport_read(base + 0x1f, 1, 1, ne2000_reset_ioport_read, s);
454 qemu_add_fd_read_handler(nd->fd, ne2000_can_receive, ne2000_receive, s);