3 void cpu_mips_irqctrl_init (void)
7 /* XXX: do not use a global */
8 uint32_t cpu_mips_get_random (CPUState *env)
10 static uint32_t seed = 0;
12 seed = seed * 314159 + 1;
13 idx = (seed >> 16) % (env->nb_tlb - env->CP0_Wired) + env->CP0_Wired;
18 uint32_t cpu_mips_get_count (CPUState *env)
20 return env->CP0_Count +
21 (uint32_t)muldiv64(qemu_get_clock(vm_clock),
22 100 * 1000 * 1000, ticks_per_sec);
25 void cpu_mips_store_count (CPUState *env, uint32_t count)
29 uint32_t compare = env->CP0_Compare;
34 now = qemu_get_clock(vm_clock);
35 next = now + muldiv64(compare - tmp, ticks_per_sec, 100 * 1000 * 1000);
40 fprintf(logfile, "%s: 0x%08" PRIx64 " %08x %08x => 0x%08" PRIx64 "\n",
41 __func__, now, count, compare, next - now);
44 /* Store new count and compare registers */
45 env->CP0_Compare = compare;
47 count - (uint32_t)muldiv64(now, 100 * 1000 * 1000, ticks_per_sec);
49 qemu_mod_timer(env->timer, next);
52 static void cpu_mips_update_count (CPUState *env, uint32_t count)
54 if (env->CP0_Cause & (1 << CP0Ca_DC))
57 cpu_mips_store_count(env, count);
60 void cpu_mips_store_compare (CPUState *env, uint32_t value)
62 env->CP0_Compare = value;
63 cpu_mips_update_count(env, cpu_mips_get_count(env));
64 if ((env->CP0_Config0 & (0x7 << CP0C0_AR)) == (1 << CP0C0_AR))
65 env->CP0_Cause &= ~(1 << CP0Ca_TI);
66 qemu_irq_lower(env->irq[7]);
69 static void mips_timer_cb (void *opaque)
76 fprintf(logfile, "%s\n", __func__);
79 cpu_mips_update_count(env, cpu_mips_get_count(env));
80 if ((env->CP0_Config0 & (0x7 << CP0C0_AR)) == (1 << CP0C0_AR))
81 env->CP0_Cause |= 1 << CP0Ca_TI;
82 qemu_irq_raise(env->irq[7]);
85 void cpu_mips_clock_init (CPUState *env)
87 env->timer = qemu_new_timer(vm_clock, &mips_timer_cb, env);
89 cpu_mips_update_count(env, 1);