2 * Motorola ColdFire MCF5206 SoC embedded peripheral emulation.
4 * Copyright (c) 2007 CodeSourcery.
6 * This code is licenced under the GPL
10 /* General purpose timer module. */
31 static void m5206_timer_update(m5206_timer_state *s)
33 if ((s->tmr & TMR_ORI) != 0 && (s->ter & TER_REF))
34 qemu_irq_raise(s->irq);
36 qemu_irq_lower(s->irq);
39 static void m5206_timer_reset(m5206_timer_state *s)
45 static void m5206_timer_recalibrate(m5206_timer_state *s)
50 ptimer_stop(s->timer);
52 if ((s->tmr & TMR_RST) == 0)
55 prescale = (s->tmr >> 8) + 1;
56 mode = (s->tmr >> 1) & 3;
60 if (mode == 3 || mode == 0)
61 cpu_abort(cpu_single_env,
62 "m5206_timer: mode %d not implemented\n", mode);
63 if ((s->tmr & TMR_FRR) == 0)
64 cpu_abort(cpu_single_env,
65 "m5206_timer: free running mode not implemented\n");
67 /* Assume 66MHz system clock. */
68 ptimer_set_freq(s->timer, 66000000 / prescale);
70 ptimer_set_limit(s->timer, s->trr, 0);
72 ptimer_run(s->timer, 0);
75 static void m5206_timer_trigger(void *opaque)
77 m5206_timer_state *s = (m5206_timer_state *)opaque;
79 m5206_timer_update(s);
82 static uint32_t m5206_timer_read(m5206_timer_state *s, uint32_t addr)
92 return s->trr - ptimer_get_count(s->timer);
100 static void m5206_timer_write(m5206_timer_state *s, uint32_t addr, uint32_t val)
104 if ((s->tmr & TMR_RST) != 0 && (val & TMR_RST) == 0) {
105 m5206_timer_reset(s);
108 m5206_timer_recalibrate(s);
112 m5206_timer_recalibrate(s);
118 ptimer_set_count(s->timer, val);
126 m5206_timer_update(s);
129 static m5206_timer_state *m5206_timer_init(qemu_irq irq)
131 m5206_timer_state *s;
134 s = (m5206_timer_state *)qemu_mallocz(sizeof(m5206_timer_state));
135 bh = qemu_bh_new(m5206_timer_trigger, s);
136 s->timer = ptimer_init(bh);
138 m5206_timer_reset(s);
142 /* System Integration Module. */
146 m5206_timer_state *timer[2];
150 uint16_t imr; /* 1 == interrupt is masked. */
155 /* Include the UART vector registers here. */
159 /* Interrupt controller. */
161 static int m5206_find_pending_irq(m5206_mbar_state *s)
170 active = s->ipr & ~s->imr;
174 for (i = 1; i < 14; i++) {
175 if (active & (1 << i)) {
176 if ((s->icr[i] & 0x1f) > level) {
177 level = s->icr[i] & 0x1f;
189 static void m5206_mbar_update(m5206_mbar_state *s)
195 irq = m5206_find_pending_irq(s);
199 level = (tmp >> 2) & 7;
215 /* Unknown vector. */
216 fprintf(stderr, "Unhandled vector for IRQ %d\n", irq);
225 m68k_set_irq_level(s->env, level, vector);
228 static void m5206_mbar_set_irq(void *opaque, int irq, int level)
230 m5206_mbar_state *s = (m5206_mbar_state *)opaque;
234 s->ipr &= ~(1 << irq);
236 m5206_mbar_update(s);
239 /* System Integration Module. */
241 static void m5206_mbar_reset(m5206_mbar_state *s)
263 static uint32_t m5206_mbar_read(m5206_mbar_state *s, uint32_t offset)
265 if (offset >= 0x100 && offset < 0x120) {
266 return m5206_timer_read(s->timer[0], offset - 0x100);
267 } else if (offset >= 0x120 && offset < 0x140) {
268 return m5206_timer_read(s->timer[1], offset - 0x120);
269 } else if (offset >= 0x140 && offset < 0x160) {
270 return mcf_uart_read(s->uart[0], offset - 0x140);
271 } else if (offset >= 0x180 && offset < 0x1a0) {
272 return mcf_uart_read(s->uart[1], offset - 0x180);
275 case 0x03: return s->scr;
276 case 0x14 ... 0x20: return s->icr[offset - 0x13];
277 case 0x36: return s->imr;
278 case 0x3a: return s->ipr;
279 case 0x40: return s->rsr;
281 case 0x42: return s->swivr;
283 /* DRAM mask register. */
284 /* FIXME: currently hardcoded to 128Mb. */
287 while (mask > ram_size)
289 return mask & 0x0ffe0000;
291 case 0x5c: return 1; /* DRAM bank 1 empty. */
292 case 0xcb: return s->par;
293 case 0x170: return s->uivr[0];
294 case 0x1b0: return s->uivr[1];
296 cpu_abort(cpu_single_env, "Bad MBAR read offset 0x%x", (int)offset);
300 static void m5206_mbar_write(m5206_mbar_state *s, uint32_t offset,
303 if (offset >= 0x100 && offset < 0x120) {
304 m5206_timer_write(s->timer[0], offset - 0x100, value);
306 } else if (offset >= 0x120 && offset < 0x140) {
307 m5206_timer_write(s->timer[1], offset - 0x120, value);
309 } else if (offset >= 0x140 && offset < 0x160) {
310 mcf_uart_write(s->uart[0], offset - 0x140, value);
312 } else if (offset >= 0x180 && offset < 0x1a0) {
313 mcf_uart_write(s->uart[1], offset - 0x180, value);
321 s->icr[offset - 0x13] = value;
322 m5206_mbar_update(s);
326 m5206_mbar_update(s);
332 /* TODO: implement watchdog. */
343 case 0x178: case 0x17c: case 0x1c8: case 0x1bc:
344 /* Not implemented: UART Output port bits. */
350 cpu_abort(cpu_single_env, "Bad MBAR write offset 0x%x", (int)offset);
355 /* Internal peripherals use a variety of register widths.
356 This lookup table allows a single routine to handle all of them. */
357 static const int m5206_mbar_width[] =
359 /* 000-040 */ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2,
360 /* 040-080 */ 1, 2, 2, 2, 4, 1, 2, 4, 1, 2, 4, 2, 2, 4, 2, 2,
361 /* 080-0c0 */ 4, 2, 2, 4, 2, 2, 4, 2, 2, 4, 2, 2, 4, 2, 2, 4,
362 /* 0c0-100 */ 2, 2, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
363 /* 100-140 */ 2, 2, 2, 2, 1, 0, 0, 0, 2, 2, 2, 2, 1, 0, 0, 0,
364 /* 140-180 */ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
365 /* 180-1c0 */ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
366 /* 1c0-200 */ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
369 static uint32_t m5206_mbar_readw(void *opaque, target_phys_addr_t offset);
370 static uint32_t m5206_mbar_readl(void *opaque, target_phys_addr_t offset);
372 static uint32_t m5206_mbar_readb(void *opaque, target_phys_addr_t offset)
374 m5206_mbar_state *s = (m5206_mbar_state *)opaque;
376 if (offset > 0x200) {
377 cpu_abort(cpu_single_env, "Bad MBAR read offset 0x%x", (int)offset);
379 if (m5206_mbar_width[offset >> 2] > 1) {
381 val = m5206_mbar_readw(opaque, offset & ~1);
382 if ((offset & 1) == 0) {
387 return m5206_mbar_read(s, offset);
390 static uint32_t m5206_mbar_readw(void *opaque, target_phys_addr_t offset)
392 m5206_mbar_state *s = (m5206_mbar_state *)opaque;
395 if (offset > 0x200) {
396 cpu_abort(cpu_single_env, "Bad MBAR read offset 0x%x", (int)offset);
398 width = m5206_mbar_width[offset >> 2];
401 val = m5206_mbar_readl(opaque, offset & ~3);
402 if ((offset & 3) == 0)
405 } else if (width < 2) {
407 val = m5206_mbar_readb(opaque, offset) << 8;
408 val |= m5206_mbar_readb(opaque, offset + 1);
411 return m5206_mbar_read(s, offset);
414 static uint32_t m5206_mbar_readl(void *opaque, target_phys_addr_t offset)
416 m5206_mbar_state *s = (m5206_mbar_state *)opaque;
419 if (offset > 0x200) {
420 cpu_abort(cpu_single_env, "Bad MBAR read offset 0x%x", (int)offset);
422 width = m5206_mbar_width[offset >> 2];
425 val = m5206_mbar_readw(opaque, offset) << 16;
426 val |= m5206_mbar_readw(opaque, offset + 2);
429 return m5206_mbar_read(s, offset);
432 static void m5206_mbar_writew(void *opaque, target_phys_addr_t offset,
434 static void m5206_mbar_writel(void *opaque, target_phys_addr_t offset,
437 static void m5206_mbar_writeb(void *opaque, target_phys_addr_t offset,
440 m5206_mbar_state *s = (m5206_mbar_state *)opaque;
443 if (offset > 0x200) {
444 cpu_abort(cpu_single_env, "Bad MBAR write offset 0x%x", (int)offset);
446 width = m5206_mbar_width[offset >> 2];
449 tmp = m5206_mbar_readw(opaque, offset & ~1);
451 tmp = (tmp & 0xff00) | value;
453 tmp = (tmp & 0x00ff) | (value << 8);
455 m5206_mbar_writew(opaque, offset & ~1, tmp);
458 m5206_mbar_write(s, offset, value);
461 static void m5206_mbar_writew(void *opaque, target_phys_addr_t offset,
464 m5206_mbar_state *s = (m5206_mbar_state *)opaque;
467 if (offset > 0x200) {
468 cpu_abort(cpu_single_env, "Bad MBAR write offset 0x%x", (int)offset);
470 width = m5206_mbar_width[offset >> 2];
473 tmp = m5206_mbar_readl(opaque, offset & ~3);
475 tmp = (tmp & 0xffff0000) | value;
477 tmp = (tmp & 0x0000ffff) | (value << 16);
479 m5206_mbar_writel(opaque, offset & ~3, tmp);
481 } else if (width < 2) {
482 m5206_mbar_writeb(opaque, offset, value >> 8);
483 m5206_mbar_writeb(opaque, offset + 1, value & 0xff);
486 m5206_mbar_write(s, offset, value);
489 static void m5206_mbar_writel(void *opaque, target_phys_addr_t offset,
492 m5206_mbar_state *s = (m5206_mbar_state *)opaque;
495 if (offset > 0x200) {
496 cpu_abort(cpu_single_env, "Bad MBAR write offset 0x%x", (int)offset);
498 width = m5206_mbar_width[offset >> 2];
500 m5206_mbar_writew(opaque, offset, value >> 16);
501 m5206_mbar_writew(opaque, offset + 2, value & 0xffff);
504 m5206_mbar_write(s, offset, value);
507 static CPUReadMemoryFunc *m5206_mbar_readfn[] = {
513 static CPUWriteMemoryFunc *m5206_mbar_writefn[] = {
519 qemu_irq *mcf5206_init(uint32_t base, CPUState *env)
525 s = (m5206_mbar_state *)qemu_mallocz(sizeof(m5206_mbar_state));
526 iomemtype = cpu_register_io_memory(0, m5206_mbar_readfn,
527 m5206_mbar_writefn, s);
528 cpu_register_physical_memory(base, 0x00001000, iomemtype);
530 pic = qemu_allocate_irqs(m5206_mbar_set_irq, s, 14);
531 s->timer[0] = m5206_timer_init(pic[9]);
532 s->timer[1] = m5206_timer_init(pic[10]);
533 s->uart[0] = mcf_uart_init(pic[12], serial_hds[0]);
534 s->uart[1] = mcf_uart_init(pic[13], serial_hds[1]);