2 * QEMU MC146818 RTC emulation
4 * Copyright (c) 2003-2004 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
29 #define RTC_SECONDS_ALARM 1
31 #define RTC_MINUTES_ALARM 3
33 #define RTC_HOURS_ALARM 5
34 #define RTC_ALARM_DONT_CARE 0xC0
36 #define RTC_DAY_OF_WEEK 6
37 #define RTC_DAY_OF_MONTH 7
46 #define REG_A_UIP 0x80
48 #define REG_B_SET 0x80
49 #define REG_B_PIE 0x40
50 #define REG_B_AIE 0x20
51 #define REG_B_UIE 0x10
54 uint8_t cmos_data[128];
58 target_phys_addr_t base;
60 QEMUTimer *periodic_timer;
61 int64_t next_periodic_time;
63 int64_t next_second_time;
64 QEMUTimer *second_timer;
65 QEMUTimer *second_timer2;
68 static void rtc_set_time(RTCState *s);
69 static void rtc_copy_date(RTCState *s);
71 static void rtc_timer_update(RTCState *s, int64_t current_time)
73 int period_code, period;
74 int64_t cur_clock, next_irq_clock;
76 period_code = s->cmos_data[RTC_REG_A] & 0x0f;
77 if (period_code != 0 &&
78 (s->cmos_data[RTC_REG_B] & REG_B_PIE)) {
81 /* period in 32 Khz cycles */
82 period = 1 << (period_code - 1);
83 /* compute 32 khz clock */
84 cur_clock = muldiv64(current_time, 32768, ticks_per_sec);
85 next_irq_clock = (cur_clock & ~(period - 1)) + period;
86 s->next_periodic_time = muldiv64(next_irq_clock, ticks_per_sec, 32768) + 1;
87 qemu_mod_timer(s->periodic_timer, s->next_periodic_time);
89 qemu_del_timer(s->periodic_timer);
93 static void rtc_periodic_timer(void *opaque)
97 rtc_timer_update(s, s->next_periodic_time);
98 s->cmos_data[RTC_REG_C] |= 0xc0;
99 qemu_irq_raise(s->irq);
102 static void cmos_ioport_write(void *opaque, uint32_t addr, uint32_t data)
104 RTCState *s = opaque;
106 if ((addr & 1) == 0) {
107 s->cmos_index = data & 0x7f;
110 printf("cmos: write index=0x%02x val=0x%02x\n",
111 s->cmos_index, data);
113 switch(s->cmos_index) {
114 case RTC_SECONDS_ALARM:
115 case RTC_MINUTES_ALARM:
116 case RTC_HOURS_ALARM:
117 /* XXX: not supported */
118 s->cmos_data[s->cmos_index] = data;
123 case RTC_DAY_OF_WEEK:
124 case RTC_DAY_OF_MONTH:
127 s->cmos_data[s->cmos_index] = data;
128 /* if in set mode, do not update the time */
129 if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
134 /* UIP bit is read only */
135 s->cmos_data[RTC_REG_A] = (data & ~REG_A_UIP) |
136 (s->cmos_data[RTC_REG_A] & REG_A_UIP);
137 rtc_timer_update(s, qemu_get_clock(vm_clock));
140 if (data & REG_B_SET) {
141 /* set mode: reset UIP mode */
142 s->cmos_data[RTC_REG_A] &= ~REG_A_UIP;
145 /* if disabling set mode, update the time */
146 if (s->cmos_data[RTC_REG_B] & REG_B_SET) {
150 s->cmos_data[RTC_REG_B] = data;
151 rtc_timer_update(s, qemu_get_clock(vm_clock));
155 /* cannot write to them */
158 s->cmos_data[s->cmos_index] = data;
164 static inline int to_bcd(RTCState *s, int a)
166 if (s->cmos_data[RTC_REG_B] & 0x04) {
169 return ((a / 10) << 4) | (a % 10);
173 static inline int from_bcd(RTCState *s, int a)
175 if (s->cmos_data[RTC_REG_B] & 0x04) {
178 return ((a >> 4) * 10) + (a & 0x0f);
182 static void rtc_set_time(RTCState *s)
184 struct tm *tm = &s->current_tm;
186 tm->tm_sec = from_bcd(s, s->cmos_data[RTC_SECONDS]);
187 tm->tm_min = from_bcd(s, s->cmos_data[RTC_MINUTES]);
188 tm->tm_hour = from_bcd(s, s->cmos_data[RTC_HOURS] & 0x7f);
189 if (!(s->cmos_data[RTC_REG_B] & 0x02) &&
190 (s->cmos_data[RTC_HOURS] & 0x80)) {
193 tm->tm_wday = from_bcd(s, s->cmos_data[RTC_DAY_OF_WEEK]);
194 tm->tm_mday = from_bcd(s, s->cmos_data[RTC_DAY_OF_MONTH]);
195 tm->tm_mon = from_bcd(s, s->cmos_data[RTC_MONTH]) - 1;
196 tm->tm_year = from_bcd(s, s->cmos_data[RTC_YEAR]) + 100;
199 static void rtc_copy_date(RTCState *s)
201 const struct tm *tm = &s->current_tm;
203 s->cmos_data[RTC_SECONDS] = to_bcd(s, tm->tm_sec);
204 s->cmos_data[RTC_MINUTES] = to_bcd(s, tm->tm_min);
205 if (s->cmos_data[RTC_REG_B] & 0x02) {
207 s->cmos_data[RTC_HOURS] = to_bcd(s, tm->tm_hour);
210 s->cmos_data[RTC_HOURS] = to_bcd(s, tm->tm_hour % 12);
211 if (tm->tm_hour >= 12)
212 s->cmos_data[RTC_HOURS] |= 0x80;
214 s->cmos_data[RTC_DAY_OF_WEEK] = to_bcd(s, tm->tm_wday);
215 s->cmos_data[RTC_DAY_OF_MONTH] = to_bcd(s, tm->tm_mday);
216 s->cmos_data[RTC_MONTH] = to_bcd(s, tm->tm_mon + 1);
217 s->cmos_data[RTC_YEAR] = to_bcd(s, tm->tm_year % 100);
220 /* month is between 0 and 11. */
221 static int get_days_in_month(int month, int year)
223 static const int days_tab[12] = {
224 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31
227 if ((unsigned )month >= 12)
231 if ((year % 4) == 0 && ((year % 100) != 0 || (year % 400) == 0))
237 /* update 'tm' to the next second */
238 static void rtc_next_second(struct tm *tm)
243 if ((unsigned)tm->tm_sec >= 60) {
246 if ((unsigned)tm->tm_min >= 60) {
249 if ((unsigned)tm->tm_hour >= 24) {
253 if ((unsigned)tm->tm_wday >= 7)
255 days_in_month = get_days_in_month(tm->tm_mon,
258 if (tm->tm_mday < 1) {
260 } else if (tm->tm_mday > days_in_month) {
263 if (tm->tm_mon >= 12) {
274 static void rtc_update_second(void *opaque)
276 RTCState *s = opaque;
279 /* if the oscillator is not in normal operation, we do not update */
280 if ((s->cmos_data[RTC_REG_A] & 0x70) != 0x20) {
281 s->next_second_time += ticks_per_sec;
282 qemu_mod_timer(s->second_timer, s->next_second_time);
284 rtc_next_second(&s->current_tm);
286 if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
287 /* update in progress bit */
288 s->cmos_data[RTC_REG_A] |= REG_A_UIP;
290 /* should be 244 us = 8 / 32768 seconds, but currently the
291 timers do not have the necessary resolution. */
292 delay = (ticks_per_sec * 1) / 100;
295 qemu_mod_timer(s->second_timer2,
296 s->next_second_time + delay);
300 static void rtc_update_second2(void *opaque)
302 RTCState *s = opaque;
304 if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
309 if (s->cmos_data[RTC_REG_B] & REG_B_AIE) {
310 if (((s->cmos_data[RTC_SECONDS_ALARM] & 0xc0) == 0xc0 ||
311 s->cmos_data[RTC_SECONDS_ALARM] == s->current_tm.tm_sec) &&
312 ((s->cmos_data[RTC_MINUTES_ALARM] & 0xc0) == 0xc0 ||
313 s->cmos_data[RTC_MINUTES_ALARM] == s->current_tm.tm_mon) &&
314 ((s->cmos_data[RTC_HOURS_ALARM] & 0xc0) == 0xc0 ||
315 s->cmos_data[RTC_HOURS_ALARM] == s->current_tm.tm_hour)) {
317 s->cmos_data[RTC_REG_C] |= 0xa0;
318 qemu_irq_raise(s->irq);
322 /* update ended interrupt */
323 if (s->cmos_data[RTC_REG_B] & REG_B_UIE) {
324 s->cmos_data[RTC_REG_C] |= 0x90;
325 qemu_irq_raise(s->irq);
328 /* clear update in progress bit */
329 s->cmos_data[RTC_REG_A] &= ~REG_A_UIP;
331 s->next_second_time += ticks_per_sec;
332 qemu_mod_timer(s->second_timer, s->next_second_time);
335 static uint32_t cmos_ioport_read(void *opaque, uint32_t addr)
337 RTCState *s = opaque;
339 if ((addr & 1) == 0) {
342 switch(s->cmos_index) {
346 case RTC_DAY_OF_WEEK:
347 case RTC_DAY_OF_MONTH:
350 ret = s->cmos_data[s->cmos_index];
353 ret = s->cmos_data[s->cmos_index];
356 ret = s->cmos_data[s->cmos_index];
357 qemu_irq_lower(s->irq);
358 s->cmos_data[RTC_REG_C] = 0x00;
361 ret = s->cmos_data[s->cmos_index];
365 printf("cmos: read index=0x%02x val=0x%02x\n",
372 void rtc_set_memory(RTCState *s, int addr, int val)
374 if (addr >= 0 && addr <= 127)
375 s->cmos_data[addr] = val;
378 void rtc_set_date(RTCState *s, const struct tm *tm)
384 /* PC cmos mappings */
385 #define REG_IBM_CENTURY_BYTE 0x32
386 #define REG_IBM_PS2_CENTURY_BYTE 0x37
388 void rtc_set_date_from_host(RTCState *s)
394 /* set the CMOS date */
402 val = to_bcd(s, (tm->tm_year / 100) + 19);
403 rtc_set_memory(s, REG_IBM_CENTURY_BYTE, val);
404 rtc_set_memory(s, REG_IBM_PS2_CENTURY_BYTE, val);
407 static void rtc_save(QEMUFile *f, void *opaque)
409 RTCState *s = opaque;
411 qemu_put_buffer(f, s->cmos_data, 128);
412 qemu_put_8s(f, &s->cmos_index);
414 qemu_put_be32s(f, &s->current_tm.tm_sec);
415 qemu_put_be32s(f, &s->current_tm.tm_min);
416 qemu_put_be32s(f, &s->current_tm.tm_hour);
417 qemu_put_be32s(f, &s->current_tm.tm_wday);
418 qemu_put_be32s(f, &s->current_tm.tm_mday);
419 qemu_put_be32s(f, &s->current_tm.tm_mon);
420 qemu_put_be32s(f, &s->current_tm.tm_year);
422 qemu_put_timer(f, s->periodic_timer);
423 qemu_put_be64s(f, &s->next_periodic_time);
425 qemu_put_be64s(f, &s->next_second_time);
426 qemu_put_timer(f, s->second_timer);
427 qemu_put_timer(f, s->second_timer2);
430 static int rtc_load(QEMUFile *f, void *opaque, int version_id)
432 RTCState *s = opaque;
437 qemu_get_buffer(f, s->cmos_data, 128);
438 qemu_get_8s(f, &s->cmos_index);
440 qemu_get_be32s(f, &s->current_tm.tm_sec);
441 qemu_get_be32s(f, &s->current_tm.tm_min);
442 qemu_get_be32s(f, &s->current_tm.tm_hour);
443 qemu_get_be32s(f, &s->current_tm.tm_wday);
444 qemu_get_be32s(f, &s->current_tm.tm_mday);
445 qemu_get_be32s(f, &s->current_tm.tm_mon);
446 qemu_get_be32s(f, &s->current_tm.tm_year);
448 qemu_get_timer(f, s->periodic_timer);
449 qemu_get_be64s(f, &s->next_periodic_time);
451 qemu_get_be64s(f, &s->next_second_time);
452 qemu_get_timer(f, s->second_timer);
453 qemu_get_timer(f, s->second_timer2);
457 RTCState *rtc_init(int base, qemu_irq irq)
461 s = qemu_mallocz(sizeof(RTCState));
466 s->cmos_data[RTC_REG_A] = 0x26;
467 s->cmos_data[RTC_REG_B] = 0x02;
468 s->cmos_data[RTC_REG_C] = 0x00;
469 s->cmos_data[RTC_REG_D] = 0x80;
471 rtc_set_date_from_host(s);
473 s->periodic_timer = qemu_new_timer(vm_clock,
474 rtc_periodic_timer, s);
475 s->second_timer = qemu_new_timer(vm_clock,
476 rtc_update_second, s);
477 s->second_timer2 = qemu_new_timer(vm_clock,
478 rtc_update_second2, s);
480 s->next_second_time = qemu_get_clock(vm_clock) + (ticks_per_sec * 99) / 100;
481 qemu_mod_timer(s->second_timer2, s->next_second_time);
483 register_ioport_write(base, 2, 1, cmos_ioport_write, s);
484 register_ioport_read(base, 2, 1, cmos_ioport_read, s);
486 register_savevm("mc146818rtc", base, 1, rtc_save, rtc_load, s);
490 /* Memory mapped interface */
491 uint32_t cmos_mm_readb (void *opaque, target_phys_addr_t addr)
493 RTCState *s = opaque;
495 return cmos_ioport_read(s, addr - s->base) & 0xFF;
498 void cmos_mm_writeb (void *opaque,
499 target_phys_addr_t addr, uint32_t value)
501 RTCState *s = opaque;
503 cmos_ioport_write(s, addr - s->base, value & 0xFF);
506 uint32_t cmos_mm_readw (void *opaque, target_phys_addr_t addr)
508 RTCState *s = opaque;
510 return cmos_ioport_read(s, addr - s->base) & 0xFFFF;
513 void cmos_mm_writew (void *opaque,
514 target_phys_addr_t addr, uint32_t value)
516 RTCState *s = opaque;
518 cmos_ioport_write(s, addr - s->base, value & 0xFFFF);
521 uint32_t cmos_mm_readl (void *opaque, target_phys_addr_t addr)
523 RTCState *s = opaque;
525 return cmos_ioport_read(s, addr - s->base);
528 void cmos_mm_writel (void *opaque,
529 target_phys_addr_t addr, uint32_t value)
531 RTCState *s = opaque;
533 cmos_ioport_write(s, addr - s->base, value);
536 static CPUReadMemoryFunc *rtc_mm_read[] = {
542 static CPUWriteMemoryFunc *rtc_mm_write[] = {
548 RTCState *rtc_mm_init(target_phys_addr_t base, qemu_irq irq)
553 s = qemu_mallocz(sizeof(RTCState));
558 s->cmos_data[RTC_REG_A] = 0x26;
559 s->cmos_data[RTC_REG_B] = 0x02;
560 s->cmos_data[RTC_REG_C] = 0x00;
561 s->cmos_data[RTC_REG_D] = 0x80;
564 rtc_set_date_from_host(s);
566 s->periodic_timer = qemu_new_timer(vm_clock,
567 rtc_periodic_timer, s);
568 s->second_timer = qemu_new_timer(vm_clock,
569 rtc_update_second, s);
570 s->second_timer2 = qemu_new_timer(vm_clock,
571 rtc_update_second2, s);
573 s->next_second_time = qemu_get_clock(vm_clock) + (ticks_per_sec * 99) / 100;
574 qemu_mod_timer(s->second_timer2, s->next_second_time);
576 io_memory = cpu_register_io_memory(0, rtc_mm_read, rtc_mm_write, s);
577 cpu_register_physical_memory(base, 2, io_memory);
579 register_savevm("mc146818rtc", base, 1, rtc_save, rtc_load, s);