2 * QEMU M48T59 NVRAM emulation for PPC PREP platform
4 * Copyright (c) 2003-2004 Jocelyn Mayer
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
29 #if defined(NVRAM_DEBUG)
30 #define NVRAM_PRINTF(fmt, args...) do { printf(fmt , ##args); } while (0)
32 #define NVRAM_PRINTF(fmt, args...) do { } while (0)
36 /* Hardware parameters */
43 /* Alarm & watchdog */
45 struct QEMUTimer *alrm_timer;
46 struct QEMUTimer *wd_timer;
52 /* Fake timer functions */
53 /* Generic helpers for BCD */
54 static inline uint8_t toBCD (uint8_t value)
56 return (((value / 10) % 10) << 4) | (value % 10);
59 static inline uint8_t fromBCD (uint8_t BCD)
61 return ((BCD >> 4) * 10) + (BCD & 0x0F);
64 /* RTC management helpers */
65 static void get_time (m48t59_t *NVRAM, struct tm *tm)
69 t = time(NULL) + NVRAM->time_offset;
73 static void set_time (m48t59_t *NVRAM, struct tm *tm)
77 new_time = mktime(tm);
79 NVRAM->time_offset = new_time - now;
82 /* Alarm management */
83 static void alarm_cb (void *opaque)
87 m48t59_t *NVRAM = opaque;
89 pic_set_irq(NVRAM->IRQ, 1);
90 if ((NVRAM->buffer[0x1FF5] & 0x80) == 0 &&
91 (NVRAM->buffer[0x1FF4] & 0x80) == 0 &&
92 (NVRAM->buffer[0x1FF3] & 0x80) == 0 &&
93 (NVRAM->buffer[0x1FF2] & 0x80) == 0) {
94 /* Repeat once a month */
95 get_time(NVRAM, &tm_now);
96 memcpy(&tm, &tm_now, sizeof(struct tm));
98 if (tm.tm_mon == 13) {
102 next_time = mktime(&tm);
103 } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 &&
104 (NVRAM->buffer[0x1FF4] & 0x80) == 0 &&
105 (NVRAM->buffer[0x1FF3] & 0x80) == 0 &&
106 (NVRAM->buffer[0x1FF2] & 0x80) == 0) {
107 /* Repeat once a day */
108 next_time = 24 * 60 * 60 + mktime(&tm_now);
109 } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 &&
110 (NVRAM->buffer[0x1FF4] & 0x80) != 0 &&
111 (NVRAM->buffer[0x1FF3] & 0x80) == 0 &&
112 (NVRAM->buffer[0x1FF2] & 0x80) == 0) {
113 /* Repeat once an hour */
114 next_time = 60 * 60 + mktime(&tm_now);
115 } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 &&
116 (NVRAM->buffer[0x1FF4] & 0x80) != 0 &&
117 (NVRAM->buffer[0x1FF3] & 0x80) != 0 &&
118 (NVRAM->buffer[0x1FF2] & 0x80) == 0) {
119 /* Repeat once a minute */
120 next_time = 60 + mktime(&tm_now);
122 /* Repeat once a second */
123 next_time = 1 + mktime(&tm_now);
125 qemu_mod_timer(NVRAM->alrm_timer, next_time * 1000);
126 pic_set_irq(NVRAM->IRQ, 0);
130 static void get_alarm (m48t59_t *NVRAM, struct tm *tm)
132 localtime_r(&NVRAM->alarm, tm);
135 static void set_alarm (m48t59_t *NVRAM, struct tm *tm)
137 NVRAM->alarm = mktime(tm);
138 if (NVRAM->alrm_timer != NULL) {
139 qemu_del_timer(NVRAM->alrm_timer);
140 NVRAM->alrm_timer = NULL;
142 if (NVRAM->alarm - time(NULL) > 0)
143 qemu_mod_timer(NVRAM->alrm_timer, NVRAM->alarm * 1000);
146 /* Watchdog management */
147 static void watchdog_cb (void *opaque)
149 m48t59_t *NVRAM = opaque;
151 NVRAM->buffer[0x1FF0] |= 0x80;
152 if (NVRAM->buffer[0x1FF7] & 0x80) {
153 NVRAM->buffer[0x1FF7] = 0x00;
154 NVRAM->buffer[0x1FFC] &= ~0x40;
157 pic_set_irq(NVRAM->IRQ, 1);
158 pic_set_irq(NVRAM->IRQ, 0);
162 static void set_up_watchdog (m48t59_t *NVRAM, uint8_t value)
164 uint64_t interval; /* in 1/16 seconds */
166 if (NVRAM->wd_timer != NULL) {
167 qemu_del_timer(NVRAM->wd_timer);
168 NVRAM->wd_timer = NULL;
170 NVRAM->buffer[0x1FF0] &= ~0x80;
172 interval = (1 << (2 * (value & 0x03))) * ((value >> 2) & 0x1F);
173 qemu_mod_timer(NVRAM->wd_timer, ((uint64_t)time(NULL) * 1000) +
174 ((interval * 1000) >> 4));
178 /* Direct access to NVRAM */
179 void m48t59_write (m48t59_t *NVRAM, uint32_t val)
184 if (NVRAM->addr > 0x1FF8 && NVRAM->addr < 0x2000)
185 NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__, NVRAM->addr, val);
186 switch (NVRAM->addr) {
188 /* flags register : read-only */
195 tmp = fromBCD(val & 0x7F);
196 if (tmp >= 0 && tmp <= 59) {
197 get_alarm(NVRAM, &tm);
199 NVRAM->buffer[0x1FF2] = val;
200 set_alarm(NVRAM, &tm);
205 tmp = fromBCD(val & 0x7F);
206 if (tmp >= 0 && tmp <= 59) {
207 get_alarm(NVRAM, &tm);
209 NVRAM->buffer[0x1FF3] = val;
210 set_alarm(NVRAM, &tm);
215 tmp = fromBCD(val & 0x3F);
216 if (tmp >= 0 && tmp <= 23) {
217 get_alarm(NVRAM, &tm);
219 NVRAM->buffer[0x1FF4] = val;
220 set_alarm(NVRAM, &tm);
225 tmp = fromBCD(val & 0x1F);
227 get_alarm(NVRAM, &tm);
229 NVRAM->buffer[0x1FF5] = val;
230 set_alarm(NVRAM, &tm);
235 NVRAM->buffer[0x1FF6] = val;
239 NVRAM->buffer[0x1FF7] = val;
240 set_up_watchdog(NVRAM, val);
244 NVRAM->buffer[0x1FF8] = (val & ~0xA0) | 0x90;
248 tmp = fromBCD(val & 0x7F);
249 if (tmp >= 0 && tmp <= 59) {
250 get_time(NVRAM, &tm);
252 set_time(NVRAM, &tm);
254 if ((val & 0x80) ^ (NVRAM->buffer[0x1FF9] & 0x80)) {
256 NVRAM->stop_time = time(NULL);
258 NVRAM->time_offset += NVRAM->stop_time - time(NULL);
259 NVRAM->stop_time = 0;
262 NVRAM->buffer[0x1FF9] = val & 0x80;
266 tmp = fromBCD(val & 0x7F);
267 if (tmp >= 0 && tmp <= 59) {
268 get_time(NVRAM, &tm);
270 set_time(NVRAM, &tm);
275 tmp = fromBCD(val & 0x3F);
276 if (tmp >= 0 && tmp <= 23) {
277 get_time(NVRAM, &tm);
279 set_time(NVRAM, &tm);
283 /* day of the week / century */
284 tmp = fromBCD(val & 0x07);
285 get_time(NVRAM, &tm);
287 set_time(NVRAM, &tm);
288 NVRAM->buffer[0x1FFC] = val & 0x40;
292 tmp = fromBCD(val & 0x1F);
294 get_time(NVRAM, &tm);
296 set_time(NVRAM, &tm);
301 tmp = fromBCD(val & 0x1F);
302 if (tmp >= 1 && tmp <= 12) {
303 get_time(NVRAM, &tm);
305 set_time(NVRAM, &tm);
311 if (tmp >= 0 && tmp <= 99) {
312 get_time(NVRAM, &tm);
313 tm.tm_year = fromBCD(val);
314 set_time(NVRAM, &tm);
318 if (NVRAM->addr < 0x1FF0 ||
319 (NVRAM->addr > 0x1FFF && NVRAM->addr < NVRAM->size)) {
320 NVRAM->buffer[NVRAM->addr] = val & 0xFF;
326 uint32_t m48t59_read (m48t59_t *NVRAM)
329 uint32_t retval = 0xFF;
331 switch (NVRAM->addr) {
355 /* A read resets the watchdog */
356 set_up_watchdog(NVRAM, NVRAM->buffer[0x1FF7]);
363 get_time(NVRAM, &tm);
364 retval = (NVRAM->buffer[0x1FF9] & 0x80) | toBCD(tm.tm_sec);
368 get_time(NVRAM, &tm);
369 retval = toBCD(tm.tm_min);
373 get_time(NVRAM, &tm);
374 retval = toBCD(tm.tm_hour);
377 /* day of the week / century */
378 get_time(NVRAM, &tm);
379 retval = NVRAM->buffer[0x1FFC] | tm.tm_wday;
383 get_time(NVRAM, &tm);
384 retval = toBCD(tm.tm_mday);
388 get_time(NVRAM, &tm);
389 retval = toBCD(tm.tm_mon + 1);
393 get_time(NVRAM, &tm);
394 retval = toBCD(tm.tm_year);
397 if (NVRAM->addr < 0x1FF0 ||
398 (NVRAM->addr > 0x1FFF && NVRAM->addr < NVRAM->size)) {
400 retval = NVRAM->buffer[NVRAM->addr];
404 if (NVRAM->addr > 0x1FF9 && NVRAM->addr < 0x2000)
405 NVRAM_PRINTF("0x%08x <= 0x%08x\n", NVRAM->addr, retval);
410 void m48t59_set_addr (m48t59_t *NVRAM, uint32_t addr)
415 /* IO access to NVRAM */
416 static void NVRAM_writeb (void *opaque, uint32_t addr, uint32_t val)
418 m48t59_t *NVRAM = opaque;
420 addr -= NVRAM->io_base;
423 NVRAM->addr &= ~0x00FF;
427 NVRAM->addr &= ~0xFF00;
428 NVRAM->addr |= val << 8;
431 m48t59_write(NVRAM, val);
432 NVRAM->addr = 0x0000;
439 static uint32_t NVRAM_readb (void *opaque, uint32_t addr)
441 m48t59_t *NVRAM = opaque;
443 if (addr == NVRAM->io_base + 3)
444 return m48t59_read(NVRAM);
449 /* Initialisation routine */
450 m48t59_t *m48t59_init (int IRQ, uint32_t io_base, uint16_t size)
454 s = qemu_mallocz(sizeof(m48t59_t));
457 s->buffer = qemu_mallocz(size);
464 s->io_base = io_base;
466 register_ioport_read(io_base, 0x04, 1, NVRAM_readb, s);
467 register_ioport_write(io_base, 0x04, 1, NVRAM_writeb, s);
468 s->alrm_timer = qemu_new_timer(vm_clock, &alarm_cb, s);
469 s->wd_timer = qemu_new_timer(vm_clock, &watchdog_cb, s);