2 * QEMU M48T59 and M48T08 NVRAM emulation for PPC PREP and Sparc platforms
4 * Copyright (c) 2003-2005, 2007 Jocelyn Mayer
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
29 #if defined(DEBUG_NVRAM)
30 #define NVRAM_PRINTF(fmt, args...) do { printf(fmt , ##args); } while (0)
32 #define NVRAM_PRINTF(fmt, args...) do { } while (0)
36 * The M48T08 and M48T59 chips are very similar. The newer '59 has
37 * alarm and a watchdog timer and related control registers. In the
38 * PPC platform there is also a nvram lock function.
41 /* Model parameters */
42 int type; // 8 = m48t08, 59 = m48t59
43 /* Hardware parameters */
46 target_phys_addr_t mem_base;
52 /* Alarm & watchdog */
54 struct QEMUTimer *alrm_timer;
55 struct QEMUTimer *wd_timer;
62 /* Fake timer functions */
63 /* Generic helpers for BCD */
64 static inline uint8_t toBCD (uint8_t value)
66 return (((value / 10) % 10) << 4) | (value % 10);
69 static inline uint8_t fromBCD (uint8_t BCD)
71 return ((BCD >> 4) * 10) + (BCD & 0x0F);
74 /* RTC management helpers */
75 static void get_time (m48t59_t *NVRAM, struct tm *tm)
79 t = time(NULL) + NVRAM->time_offset;
81 memcpy(tm,localtime(&t),sizeof(*tm));
86 localtime_r (&t, tm) ;
90 static void set_time (m48t59_t *NVRAM, struct tm *tm)
94 new_time = mktime(tm);
96 NVRAM->time_offset = new_time - now;
99 /* Alarm management */
100 static void alarm_cb (void *opaque)
102 struct tm tm, tm_now;
104 m48t59_t *NVRAM = opaque;
106 qemu_set_irq(NVRAM->IRQ, 1);
107 if ((NVRAM->buffer[0x1FF5] & 0x80) == 0 &&
108 (NVRAM->buffer[0x1FF4] & 0x80) == 0 &&
109 (NVRAM->buffer[0x1FF3] & 0x80) == 0 &&
110 (NVRAM->buffer[0x1FF2] & 0x80) == 0) {
111 /* Repeat once a month */
112 get_time(NVRAM, &tm_now);
113 memcpy(&tm, &tm_now, sizeof(struct tm));
115 if (tm.tm_mon == 13) {
119 next_time = mktime(&tm);
120 } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 &&
121 (NVRAM->buffer[0x1FF4] & 0x80) == 0 &&
122 (NVRAM->buffer[0x1FF3] & 0x80) == 0 &&
123 (NVRAM->buffer[0x1FF2] & 0x80) == 0) {
124 /* Repeat once a day */
125 next_time = 24 * 60 * 60 + mktime(&tm_now);
126 } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 &&
127 (NVRAM->buffer[0x1FF4] & 0x80) != 0 &&
128 (NVRAM->buffer[0x1FF3] & 0x80) == 0 &&
129 (NVRAM->buffer[0x1FF2] & 0x80) == 0) {
130 /* Repeat once an hour */
131 next_time = 60 * 60 + mktime(&tm_now);
132 } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 &&
133 (NVRAM->buffer[0x1FF4] & 0x80) != 0 &&
134 (NVRAM->buffer[0x1FF3] & 0x80) != 0 &&
135 (NVRAM->buffer[0x1FF2] & 0x80) == 0) {
136 /* Repeat once a minute */
137 next_time = 60 + mktime(&tm_now);
139 /* Repeat once a second */
140 next_time = 1 + mktime(&tm_now);
142 qemu_mod_timer(NVRAM->alrm_timer, next_time * 1000);
143 qemu_set_irq(NVRAM->IRQ, 0);
147 static void get_alarm (m48t59_t *NVRAM, struct tm *tm)
150 memcpy(tm,localtime(&NVRAM->alarm),sizeof(*tm));
153 gmtime_r (&NVRAM->alarm, tm);
155 localtime_r (&NVRAM->alarm, tm);
159 static void set_alarm (m48t59_t *NVRAM, struct tm *tm)
161 NVRAM->alarm = mktime(tm);
162 if (NVRAM->alrm_timer != NULL) {
163 qemu_del_timer(NVRAM->alrm_timer);
164 NVRAM->alrm_timer = NULL;
166 if (NVRAM->alarm - time(NULL) > 0)
167 qemu_mod_timer(NVRAM->alrm_timer, NVRAM->alarm * 1000);
170 /* Watchdog management */
171 static void watchdog_cb (void *opaque)
173 m48t59_t *NVRAM = opaque;
175 NVRAM->buffer[0x1FF0] |= 0x80;
176 if (NVRAM->buffer[0x1FF7] & 0x80) {
177 NVRAM->buffer[0x1FF7] = 0x00;
178 NVRAM->buffer[0x1FFC] &= ~0x40;
179 /* May it be a hw CPU Reset instead ? */
180 qemu_system_reset_request();
182 qemu_set_irq(NVRAM->IRQ, 1);
183 qemu_set_irq(NVRAM->IRQ, 0);
187 static void set_up_watchdog (m48t59_t *NVRAM, uint8_t value)
189 uint64_t interval; /* in 1/16 seconds */
191 if (NVRAM->wd_timer != NULL) {
192 qemu_del_timer(NVRAM->wd_timer);
193 NVRAM->wd_timer = NULL;
195 NVRAM->buffer[0x1FF0] &= ~0x80;
197 interval = (1 << (2 * (value & 0x03))) * ((value >> 2) & 0x1F);
198 qemu_mod_timer(NVRAM->wd_timer, ((uint64_t)time(NULL) * 1000) +
199 ((interval * 1000) >> 4));
203 /* Direct access to NVRAM */
204 void m48t59_write (m48t59_t *NVRAM, uint32_t addr, uint32_t val)
209 if (addr > 0x1FF8 && addr < 0x2000)
210 NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__, addr, val);
211 if (NVRAM->type == 8 &&
212 (addr >= 0x1ff0 && addr <= 0x1ff7))
216 /* flags register : read-only */
223 tmp = fromBCD(val & 0x7F);
224 if (tmp >= 0 && tmp <= 59) {
225 get_alarm(NVRAM, &tm);
227 NVRAM->buffer[0x1FF2] = val;
228 set_alarm(NVRAM, &tm);
233 tmp = fromBCD(val & 0x7F);
234 if (tmp >= 0 && tmp <= 59) {
235 get_alarm(NVRAM, &tm);
237 NVRAM->buffer[0x1FF3] = val;
238 set_alarm(NVRAM, &tm);
243 tmp = fromBCD(val & 0x3F);
244 if (tmp >= 0 && tmp <= 23) {
245 get_alarm(NVRAM, &tm);
247 NVRAM->buffer[0x1FF4] = val;
248 set_alarm(NVRAM, &tm);
253 tmp = fromBCD(val & 0x1F);
255 get_alarm(NVRAM, &tm);
257 NVRAM->buffer[0x1FF5] = val;
258 set_alarm(NVRAM, &tm);
263 NVRAM->buffer[0x1FF6] = val;
267 NVRAM->buffer[0x1FF7] = val;
268 set_up_watchdog(NVRAM, val);
272 NVRAM->buffer[0x1FF8] = (val & ~0xA0) | 0x90;
276 tmp = fromBCD(val & 0x7F);
277 if (tmp >= 0 && tmp <= 59) {
278 get_time(NVRAM, &tm);
280 set_time(NVRAM, &tm);
282 if ((val & 0x80) ^ (NVRAM->buffer[0x1FF9] & 0x80)) {
284 NVRAM->stop_time = time(NULL);
286 NVRAM->time_offset += NVRAM->stop_time - time(NULL);
287 NVRAM->stop_time = 0;
290 NVRAM->buffer[0x1FF9] = val & 0x80;
294 tmp = fromBCD(val & 0x7F);
295 if (tmp >= 0 && tmp <= 59) {
296 get_time(NVRAM, &tm);
298 set_time(NVRAM, &tm);
303 tmp = fromBCD(val & 0x3F);
304 if (tmp >= 0 && tmp <= 23) {
305 get_time(NVRAM, &tm);
307 set_time(NVRAM, &tm);
311 /* day of the week / century */
312 tmp = fromBCD(val & 0x07);
313 get_time(NVRAM, &tm);
315 set_time(NVRAM, &tm);
316 NVRAM->buffer[0x1FFC] = val & 0x40;
320 tmp = fromBCD(val & 0x1F);
322 get_time(NVRAM, &tm);
324 set_time(NVRAM, &tm);
329 tmp = fromBCD(val & 0x1F);
330 if (tmp >= 1 && tmp <= 12) {
331 get_time(NVRAM, &tm);
333 set_time(NVRAM, &tm);
339 if (tmp >= 0 && tmp <= 99) {
340 get_time(NVRAM, &tm);
341 if (NVRAM->type == 8)
342 tm.tm_year = fromBCD(val) + 68; // Base year is 1968
344 tm.tm_year = fromBCD(val);
345 set_time(NVRAM, &tm);
349 /* Check lock registers state */
350 if (addr >= 0x20 && addr <= 0x2F && (NVRAM->lock & 1))
352 if (addr >= 0x30 && addr <= 0x3F && (NVRAM->lock & 2))
355 if (addr < NVRAM->size) {
356 NVRAM->buffer[addr] = val & 0xFF;
362 uint32_t m48t59_read (m48t59_t *NVRAM, uint32_t addr)
365 uint32_t retval = 0xFF;
367 if (NVRAM->type == 8 &&
368 (addr >= 0x1ff0 && addr <= 0x1ff7))
394 /* A read resets the watchdog */
395 set_up_watchdog(NVRAM, NVRAM->buffer[0x1FF7]);
402 get_time(NVRAM, &tm);
403 retval = (NVRAM->buffer[0x1FF9] & 0x80) | toBCD(tm.tm_sec);
407 get_time(NVRAM, &tm);
408 retval = toBCD(tm.tm_min);
412 get_time(NVRAM, &tm);
413 retval = toBCD(tm.tm_hour);
416 /* day of the week / century */
417 get_time(NVRAM, &tm);
418 retval = NVRAM->buffer[0x1FFC] | tm.tm_wday;
422 get_time(NVRAM, &tm);
423 retval = toBCD(tm.tm_mday);
427 get_time(NVRAM, &tm);
428 retval = toBCD(tm.tm_mon + 1);
432 get_time(NVRAM, &tm);
433 if (NVRAM->type == 8)
434 retval = toBCD(tm.tm_year - 68); // Base year is 1968
436 retval = toBCD(tm.tm_year);
439 /* Check lock registers state */
440 if (addr >= 0x20 && addr <= 0x2F && (NVRAM->lock & 1))
442 if (addr >= 0x30 && addr <= 0x3F && (NVRAM->lock & 2))
445 if (addr < NVRAM->size) {
446 retval = NVRAM->buffer[addr];
450 if (addr > 0x1FF9 && addr < 0x2000)
451 NVRAM_PRINTF("0x%08x <= 0x%08x\n", addr, retval);
456 void m48t59_set_addr (m48t59_t *NVRAM, uint32_t addr)
461 void m48t59_toggle_lock (m48t59_t *NVRAM, int lock)
463 NVRAM->lock ^= 1 << lock;
466 /* IO access to NVRAM */
467 static void NVRAM_writeb (void *opaque, uint32_t addr, uint32_t val)
469 m48t59_t *NVRAM = opaque;
471 addr -= NVRAM->io_base;
472 NVRAM_PRINTF("0x%08x => 0x%08x\n", addr, val);
475 NVRAM->addr &= ~0x00FF;
479 NVRAM->addr &= ~0xFF00;
480 NVRAM->addr |= val << 8;
483 m48t59_write(NVRAM, val, NVRAM->addr);
484 NVRAM->addr = 0x0000;
491 static uint32_t NVRAM_readb (void *opaque, uint32_t addr)
493 m48t59_t *NVRAM = opaque;
496 addr -= NVRAM->io_base;
499 retval = m48t59_read(NVRAM, NVRAM->addr);
505 NVRAM_PRINTF("0x%08x <= 0x%08x\n", addr, retval);
510 static void nvram_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)
512 m48t59_t *NVRAM = opaque;
514 addr -= NVRAM->mem_base;
515 m48t59_write(NVRAM, addr, value & 0xff);
518 static void nvram_writew (void *opaque, target_phys_addr_t addr, uint32_t value)
520 m48t59_t *NVRAM = opaque;
522 addr -= NVRAM->mem_base;
523 m48t59_write(NVRAM, addr, (value >> 8) & 0xff);
524 m48t59_write(NVRAM, addr + 1, value & 0xff);
527 static void nvram_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
529 m48t59_t *NVRAM = opaque;
531 addr -= NVRAM->mem_base;
532 m48t59_write(NVRAM, addr, (value >> 24) & 0xff);
533 m48t59_write(NVRAM, addr + 1, (value >> 16) & 0xff);
534 m48t59_write(NVRAM, addr + 2, (value >> 8) & 0xff);
535 m48t59_write(NVRAM, addr + 3, value & 0xff);
538 static uint32_t nvram_readb (void *opaque, target_phys_addr_t addr)
540 m48t59_t *NVRAM = opaque;
543 addr -= NVRAM->mem_base;
544 retval = m48t59_read(NVRAM, addr);
548 static uint32_t nvram_readw (void *opaque, target_phys_addr_t addr)
550 m48t59_t *NVRAM = opaque;
553 addr -= NVRAM->mem_base;
554 retval = m48t59_read(NVRAM, addr) << 8;
555 retval |= m48t59_read(NVRAM, addr + 1);
559 static uint32_t nvram_readl (void *opaque, target_phys_addr_t addr)
561 m48t59_t *NVRAM = opaque;
564 addr -= NVRAM->mem_base;
565 retval = m48t59_read(NVRAM, addr) << 24;
566 retval |= m48t59_read(NVRAM, addr + 1) << 16;
567 retval |= m48t59_read(NVRAM, addr + 2) << 8;
568 retval |= m48t59_read(NVRAM, addr + 3);
572 static CPUWriteMemoryFunc *nvram_write[] = {
578 static CPUReadMemoryFunc *nvram_read[] = {
584 static void m48t59_save(QEMUFile *f, void *opaque)
586 m48t59_t *s = opaque;
588 qemu_put_8s(f, &s->lock);
589 qemu_put_be16s(f, &s->addr);
590 qemu_put_buffer(f, s->buffer, s->size);
593 static int m48t59_load(QEMUFile *f, void *opaque, int version_id)
595 m48t59_t *s = opaque;
600 qemu_get_8s(f, &s->lock);
601 qemu_get_be16s(f, &s->addr);
602 qemu_get_buffer(f, s->buffer, s->size);
607 static void m48t59_reset(void *opaque)
609 m48t59_t *NVRAM = opaque;
611 if (NVRAM->alrm_timer != NULL)
612 qemu_del_timer(NVRAM->alrm_timer);
614 if (NVRAM->wd_timer != NULL)
615 qemu_del_timer(NVRAM->wd_timer);
618 /* Initialisation routine */
619 m48t59_t *m48t59_init (qemu_irq IRQ, target_phys_addr_t mem_base,
620 uint32_t io_base, uint16_t size,
624 target_phys_addr_t save_base;
626 s = qemu_mallocz(sizeof(m48t59_t));
629 s->buffer = qemu_mallocz(size);
636 s->mem_base = mem_base;
637 s->io_base = io_base;
641 register_ioport_read(io_base, 0x04, 1, NVRAM_readb, s);
642 register_ioport_write(io_base, 0x04, 1, NVRAM_writeb, s);
645 s->mem_index = cpu_register_io_memory(0, nvram_read, nvram_write, s);
646 cpu_register_physical_memory(mem_base, 0x4000, s->mem_index);
649 s->alrm_timer = qemu_new_timer(vm_clock, &alarm_cb, s);
650 s->wd_timer = qemu_new_timer(vm_clock, &watchdog_cb, s);
654 qemu_register_reset(m48t59_reset, s);
655 save_base = mem_base ? mem_base : io_base;
656 register_savevm("m48t59", save_base, 1, m48t59_save, m48t59_load, s);