2 * QEMU M48T59 NVRAM emulation for PPC PREP platform
4 * Copyright (c) 2003-2004 Jocelyn Mayer
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
29 #if defined(DEBUG_NVRAM)
30 #define NVRAM_PRINTF(fmt, args...) do { printf(fmt , ##args); } while (0)
32 #define NVRAM_PRINTF(fmt, args...) do { } while (0)
36 /* Hardware parameters */
43 /* Alarm & watchdog */
45 struct QEMUTimer *alrm_timer;
46 struct QEMUTimer *wd_timer;
53 /* Fake timer functions */
54 /* Generic helpers for BCD */
55 static inline uint8_t toBCD (uint8_t value)
57 return (((value / 10) % 10) << 4) | (value % 10);
60 static inline uint8_t fromBCD (uint8_t BCD)
62 return ((BCD >> 4) * 10) + (BCD & 0x0F);
65 /* RTC management helpers */
66 static void get_time (m48t59_t *NVRAM, struct tm *tm)
70 t = time(NULL) + NVRAM->time_offset;
72 memcpy(tm,localtime(&t),sizeof(*tm));
74 localtime_r (&t, tm) ;
78 static void set_time (m48t59_t *NVRAM, struct tm *tm)
82 new_time = mktime(tm);
84 NVRAM->time_offset = new_time - now;
87 /* Alarm management */
88 static void alarm_cb (void *opaque)
92 m48t59_t *NVRAM = opaque;
94 pic_set_irq(NVRAM->IRQ, 1);
95 if ((NVRAM->buffer[0x1FF5] & 0x80) == 0 &&
96 (NVRAM->buffer[0x1FF4] & 0x80) == 0 &&
97 (NVRAM->buffer[0x1FF3] & 0x80) == 0 &&
98 (NVRAM->buffer[0x1FF2] & 0x80) == 0) {
99 /* Repeat once a month */
100 get_time(NVRAM, &tm_now);
101 memcpy(&tm, &tm_now, sizeof(struct tm));
103 if (tm.tm_mon == 13) {
107 next_time = mktime(&tm);
108 } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 &&
109 (NVRAM->buffer[0x1FF4] & 0x80) == 0 &&
110 (NVRAM->buffer[0x1FF3] & 0x80) == 0 &&
111 (NVRAM->buffer[0x1FF2] & 0x80) == 0) {
112 /* Repeat once a day */
113 next_time = 24 * 60 * 60 + mktime(&tm_now);
114 } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 &&
115 (NVRAM->buffer[0x1FF4] & 0x80) != 0 &&
116 (NVRAM->buffer[0x1FF3] & 0x80) == 0 &&
117 (NVRAM->buffer[0x1FF2] & 0x80) == 0) {
118 /* Repeat once an hour */
119 next_time = 60 * 60 + mktime(&tm_now);
120 } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 &&
121 (NVRAM->buffer[0x1FF4] & 0x80) != 0 &&
122 (NVRAM->buffer[0x1FF3] & 0x80) != 0 &&
123 (NVRAM->buffer[0x1FF2] & 0x80) == 0) {
124 /* Repeat once a minute */
125 next_time = 60 + mktime(&tm_now);
127 /* Repeat once a second */
128 next_time = 1 + mktime(&tm_now);
130 qemu_mod_timer(NVRAM->alrm_timer, next_time * 1000);
131 pic_set_irq(NVRAM->IRQ, 0);
135 static void get_alarm (m48t59_t *NVRAM, struct tm *tm)
138 memcpy(tm,localtime(&NVRAM->alarm),sizeof(*tm));
140 localtime_r (&NVRAM->alarm, tm);
144 static void set_alarm (m48t59_t *NVRAM, struct tm *tm)
146 NVRAM->alarm = mktime(tm);
147 if (NVRAM->alrm_timer != NULL) {
148 qemu_del_timer(NVRAM->alrm_timer);
149 NVRAM->alrm_timer = NULL;
151 if (NVRAM->alarm - time(NULL) > 0)
152 qemu_mod_timer(NVRAM->alrm_timer, NVRAM->alarm * 1000);
155 /* Watchdog management */
156 static void watchdog_cb (void *opaque)
158 m48t59_t *NVRAM = opaque;
160 NVRAM->buffer[0x1FF0] |= 0x80;
161 if (NVRAM->buffer[0x1FF7] & 0x80) {
162 NVRAM->buffer[0x1FF7] = 0x00;
163 NVRAM->buffer[0x1FFC] &= ~0x40;
164 /* May it be a hw CPU Reset instead ? */
166 printf("Watchdog reset...\n");
167 cpu_interrupt(cpu_single_env, CPU_INTERRUPT_EXIT);
169 pic_set_irq(NVRAM->IRQ, 1);
170 pic_set_irq(NVRAM->IRQ, 0);
174 static void set_up_watchdog (m48t59_t *NVRAM, uint8_t value)
176 uint64_t interval; /* in 1/16 seconds */
178 if (NVRAM->wd_timer != NULL) {
179 qemu_del_timer(NVRAM->wd_timer);
180 NVRAM->wd_timer = NULL;
182 NVRAM->buffer[0x1FF0] &= ~0x80;
184 interval = (1 << (2 * (value & 0x03))) * ((value >> 2) & 0x1F);
185 qemu_mod_timer(NVRAM->wd_timer, ((uint64_t)time(NULL) * 1000) +
186 ((interval * 1000) >> 4));
190 /* Direct access to NVRAM */
191 void m48t59_write (m48t59_t *NVRAM, uint32_t val)
196 if (NVRAM->addr > 0x1FF8 && NVRAM->addr < 0x2000)
197 NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__, NVRAM->addr, val);
198 switch (NVRAM->addr) {
200 /* flags register : read-only */
207 tmp = fromBCD(val & 0x7F);
208 if (tmp >= 0 && tmp <= 59) {
209 get_alarm(NVRAM, &tm);
211 NVRAM->buffer[0x1FF2] = val;
212 set_alarm(NVRAM, &tm);
217 tmp = fromBCD(val & 0x7F);
218 if (tmp >= 0 && tmp <= 59) {
219 get_alarm(NVRAM, &tm);
221 NVRAM->buffer[0x1FF3] = val;
222 set_alarm(NVRAM, &tm);
227 tmp = fromBCD(val & 0x3F);
228 if (tmp >= 0 && tmp <= 23) {
229 get_alarm(NVRAM, &tm);
231 NVRAM->buffer[0x1FF4] = val;
232 set_alarm(NVRAM, &tm);
237 tmp = fromBCD(val & 0x1F);
239 get_alarm(NVRAM, &tm);
241 NVRAM->buffer[0x1FF5] = val;
242 set_alarm(NVRAM, &tm);
247 NVRAM->buffer[0x1FF6] = val;
251 NVRAM->buffer[0x1FF7] = val;
252 set_up_watchdog(NVRAM, val);
256 NVRAM->buffer[0x1FF8] = (val & ~0xA0) | 0x90;
260 tmp = fromBCD(val & 0x7F);
261 if (tmp >= 0 && tmp <= 59) {
262 get_time(NVRAM, &tm);
264 set_time(NVRAM, &tm);
266 if ((val & 0x80) ^ (NVRAM->buffer[0x1FF9] & 0x80)) {
268 NVRAM->stop_time = time(NULL);
270 NVRAM->time_offset += NVRAM->stop_time - time(NULL);
271 NVRAM->stop_time = 0;
274 NVRAM->buffer[0x1FF9] = val & 0x80;
278 tmp = fromBCD(val & 0x7F);
279 if (tmp >= 0 && tmp <= 59) {
280 get_time(NVRAM, &tm);
282 set_time(NVRAM, &tm);
287 tmp = fromBCD(val & 0x3F);
288 if (tmp >= 0 && tmp <= 23) {
289 get_time(NVRAM, &tm);
291 set_time(NVRAM, &tm);
295 /* day of the week / century */
296 tmp = fromBCD(val & 0x07);
297 get_time(NVRAM, &tm);
299 set_time(NVRAM, &tm);
300 NVRAM->buffer[0x1FFC] = val & 0x40;
304 tmp = fromBCD(val & 0x1F);
306 get_time(NVRAM, &tm);
308 set_time(NVRAM, &tm);
313 tmp = fromBCD(val & 0x1F);
314 if (tmp >= 1 && tmp <= 12) {
315 get_time(NVRAM, &tm);
317 set_time(NVRAM, &tm);
323 if (tmp >= 0 && tmp <= 99) {
324 get_time(NVRAM, &tm);
325 tm.tm_year = fromBCD(val);
326 set_time(NVRAM, &tm);
330 /* Check lock registers state */
331 if (NVRAM->addr >= 0x20 && NVRAM->addr <= 0x2F && (NVRAM->lock & 1))
333 if (NVRAM->addr >= 0x30 && NVRAM->addr <= 0x3F && (NVRAM->lock & 2))
335 if (NVRAM->addr < 0x1FF0 ||
336 (NVRAM->addr > 0x1FFF && NVRAM->addr < NVRAM->size)) {
337 NVRAM->buffer[NVRAM->addr] = val & 0xFF;
343 uint32_t m48t59_read (m48t59_t *NVRAM)
346 uint32_t retval = 0xFF;
348 switch (NVRAM->addr) {
372 /* A read resets the watchdog */
373 set_up_watchdog(NVRAM, NVRAM->buffer[0x1FF7]);
380 get_time(NVRAM, &tm);
381 retval = (NVRAM->buffer[0x1FF9] & 0x80) | toBCD(tm.tm_sec);
385 get_time(NVRAM, &tm);
386 retval = toBCD(tm.tm_min);
390 get_time(NVRAM, &tm);
391 retval = toBCD(tm.tm_hour);
394 /* day of the week / century */
395 get_time(NVRAM, &tm);
396 retval = NVRAM->buffer[0x1FFC] | tm.tm_wday;
400 get_time(NVRAM, &tm);
401 retval = toBCD(tm.tm_mday);
405 get_time(NVRAM, &tm);
406 retval = toBCD(tm.tm_mon + 1);
410 get_time(NVRAM, &tm);
411 retval = toBCD(tm.tm_year);
414 /* Check lock registers state */
415 if (NVRAM->addr >= 0x20 && NVRAM->addr <= 0x2F && (NVRAM->lock & 1))
417 if (NVRAM->addr >= 0x30 && NVRAM->addr <= 0x3F && (NVRAM->lock & 2))
419 if (NVRAM->addr < 0x1FF0 ||
420 (NVRAM->addr > 0x1FFF && NVRAM->addr < NVRAM->size)) {
422 retval = NVRAM->buffer[NVRAM->addr];
426 if (NVRAM->addr > 0x1FF9 && NVRAM->addr < 0x2000)
427 NVRAM_PRINTF("0x%08x <= 0x%08x\n", NVRAM->addr, retval);
432 void m48t59_set_addr (m48t59_t *NVRAM, uint32_t addr)
437 void m48t59_toggle_lock (m48t59_t *NVRAM, int lock)
439 NVRAM->lock ^= 1 << lock;
442 /* IO access to NVRAM */
443 static void NVRAM_writeb (void *opaque, uint32_t addr, uint32_t val)
445 m48t59_t *NVRAM = opaque;
447 addr -= NVRAM->io_base;
448 NVRAM_PRINTF("0x%08x => 0x%08x\n", addr, val);
451 NVRAM->addr &= ~0x00FF;
455 NVRAM->addr &= ~0xFF00;
456 NVRAM->addr |= val << 8;
459 m48t59_write(NVRAM, val);
460 NVRAM->addr = 0x0000;
467 static uint32_t NVRAM_readb (void *opaque, uint32_t addr)
469 m48t59_t *NVRAM = opaque;
472 addr -= NVRAM->io_base;
475 retval = m48t59_read(NVRAM);
481 NVRAM_PRINTF("0x%08x <= 0x%08x\n", addr, retval);
486 /* Initialisation routine */
487 m48t59_t *m48t59_init (int IRQ, uint32_t io_base, uint16_t size)
491 s = qemu_mallocz(sizeof(m48t59_t));
494 s->buffer = qemu_mallocz(size);
501 s->io_base = io_base;
503 register_ioport_read(io_base, 0x04, 1, NVRAM_readb, s);
504 register_ioport_write(io_base, 0x04, 1, NVRAM_writeb, s);
505 s->alrm_timer = qemu_new_timer(vm_clock, &alarm_cb, s);
506 s->wd_timer = qemu_new_timer(vm_clock, &watchdog_cb, s);