2 * QEMU M48T59 NVRAM emulation for PPC PREP platform
4 * Copyright (c) 2003-2004 Jocelyn Mayer
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
29 #if defined(DEBUG_NVRAM)
30 #define NVRAM_PRINTF(fmt, args...) do { printf(fmt , ##args); } while (0)
32 #define NVRAM_PRINTF(fmt, args...) do { } while (0)
36 /* Hardware parameters */
43 /* Alarm & watchdog */
45 struct QEMUTimer *alrm_timer;
46 struct QEMUTimer *wd_timer;
53 /* Fake timer functions */
54 /* Generic helpers for BCD */
55 static inline uint8_t toBCD (uint8_t value)
57 return (((value / 10) % 10) << 4) | (value % 10);
60 static inline uint8_t fromBCD (uint8_t BCD)
62 return ((BCD >> 4) * 10) + (BCD & 0x0F);
65 /* RTC management helpers */
66 static void get_time (m48t59_t *NVRAM, struct tm *tm)
70 t = time(NULL) + NVRAM->time_offset;
74 static void set_time (m48t59_t *NVRAM, struct tm *tm)
78 new_time = mktime(tm);
80 NVRAM->time_offset = new_time - now;
83 /* Alarm management */
84 static void alarm_cb (void *opaque)
88 m48t59_t *NVRAM = opaque;
90 pic_set_irq(NVRAM->IRQ, 1);
91 if ((NVRAM->buffer[0x1FF5] & 0x80) == 0 &&
92 (NVRAM->buffer[0x1FF4] & 0x80) == 0 &&
93 (NVRAM->buffer[0x1FF3] & 0x80) == 0 &&
94 (NVRAM->buffer[0x1FF2] & 0x80) == 0) {
95 /* Repeat once a month */
96 get_time(NVRAM, &tm_now);
97 memcpy(&tm, &tm_now, sizeof(struct tm));
99 if (tm.tm_mon == 13) {
103 next_time = mktime(&tm);
104 } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 &&
105 (NVRAM->buffer[0x1FF4] & 0x80) == 0 &&
106 (NVRAM->buffer[0x1FF3] & 0x80) == 0 &&
107 (NVRAM->buffer[0x1FF2] & 0x80) == 0) {
108 /* Repeat once a day */
109 next_time = 24 * 60 * 60 + mktime(&tm_now);
110 } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 &&
111 (NVRAM->buffer[0x1FF4] & 0x80) != 0 &&
112 (NVRAM->buffer[0x1FF3] & 0x80) == 0 &&
113 (NVRAM->buffer[0x1FF2] & 0x80) == 0) {
114 /* Repeat once an hour */
115 next_time = 60 * 60 + mktime(&tm_now);
116 } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 &&
117 (NVRAM->buffer[0x1FF4] & 0x80) != 0 &&
118 (NVRAM->buffer[0x1FF3] & 0x80) != 0 &&
119 (NVRAM->buffer[0x1FF2] & 0x80) == 0) {
120 /* Repeat once a minute */
121 next_time = 60 + mktime(&tm_now);
123 /* Repeat once a second */
124 next_time = 1 + mktime(&tm_now);
126 qemu_mod_timer(NVRAM->alrm_timer, next_time * 1000);
127 pic_set_irq(NVRAM->IRQ, 0);
131 static void get_alarm (m48t59_t *NVRAM, struct tm *tm)
133 localtime_r(&NVRAM->alarm, tm);
136 static void set_alarm (m48t59_t *NVRAM, struct tm *tm)
138 NVRAM->alarm = mktime(tm);
139 if (NVRAM->alrm_timer != NULL) {
140 qemu_del_timer(NVRAM->alrm_timer);
141 NVRAM->alrm_timer = NULL;
143 if (NVRAM->alarm - time(NULL) > 0)
144 qemu_mod_timer(NVRAM->alrm_timer, NVRAM->alarm * 1000);
147 /* Watchdog management */
148 static void watchdog_cb (void *opaque)
150 m48t59_t *NVRAM = opaque;
152 NVRAM->buffer[0x1FF0] |= 0x80;
153 if (NVRAM->buffer[0x1FF7] & 0x80) {
154 NVRAM->buffer[0x1FF7] = 0x00;
155 NVRAM->buffer[0x1FFC] &= ~0x40;
156 /* May it be a hw CPU Reset instead ? */
158 printf("Watchdog reset...\n");
159 cpu_interrupt(cpu_single_env, CPU_INTERRUPT_EXIT);
161 pic_set_irq(NVRAM->IRQ, 1);
162 pic_set_irq(NVRAM->IRQ, 0);
166 static void set_up_watchdog (m48t59_t *NVRAM, uint8_t value)
168 uint64_t interval; /* in 1/16 seconds */
170 if (NVRAM->wd_timer != NULL) {
171 qemu_del_timer(NVRAM->wd_timer);
172 NVRAM->wd_timer = NULL;
174 NVRAM->buffer[0x1FF0] &= ~0x80;
176 interval = (1 << (2 * (value & 0x03))) * ((value >> 2) & 0x1F);
177 qemu_mod_timer(NVRAM->wd_timer, ((uint64_t)time(NULL) * 1000) +
178 ((interval * 1000) >> 4));
182 /* Direct access to NVRAM */
183 void m48t59_write (m48t59_t *NVRAM, uint32_t val)
188 if (NVRAM->addr > 0x1FF8 && NVRAM->addr < 0x2000)
189 NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__, NVRAM->addr, val);
190 switch (NVRAM->addr) {
192 /* flags register : read-only */
199 tmp = fromBCD(val & 0x7F);
200 if (tmp >= 0 && tmp <= 59) {
201 get_alarm(NVRAM, &tm);
203 NVRAM->buffer[0x1FF2] = val;
204 set_alarm(NVRAM, &tm);
209 tmp = fromBCD(val & 0x7F);
210 if (tmp >= 0 && tmp <= 59) {
211 get_alarm(NVRAM, &tm);
213 NVRAM->buffer[0x1FF3] = val;
214 set_alarm(NVRAM, &tm);
219 tmp = fromBCD(val & 0x3F);
220 if (tmp >= 0 && tmp <= 23) {
221 get_alarm(NVRAM, &tm);
223 NVRAM->buffer[0x1FF4] = val;
224 set_alarm(NVRAM, &tm);
229 tmp = fromBCD(val & 0x1F);
231 get_alarm(NVRAM, &tm);
233 NVRAM->buffer[0x1FF5] = val;
234 set_alarm(NVRAM, &tm);
239 NVRAM->buffer[0x1FF6] = val;
243 NVRAM->buffer[0x1FF7] = val;
244 set_up_watchdog(NVRAM, val);
248 NVRAM->buffer[0x1FF8] = (val & ~0xA0) | 0x90;
252 tmp = fromBCD(val & 0x7F);
253 if (tmp >= 0 && tmp <= 59) {
254 get_time(NVRAM, &tm);
256 set_time(NVRAM, &tm);
258 if ((val & 0x80) ^ (NVRAM->buffer[0x1FF9] & 0x80)) {
260 NVRAM->stop_time = time(NULL);
262 NVRAM->time_offset += NVRAM->stop_time - time(NULL);
263 NVRAM->stop_time = 0;
266 NVRAM->buffer[0x1FF9] = val & 0x80;
270 tmp = fromBCD(val & 0x7F);
271 if (tmp >= 0 && tmp <= 59) {
272 get_time(NVRAM, &tm);
274 set_time(NVRAM, &tm);
279 tmp = fromBCD(val & 0x3F);
280 if (tmp >= 0 && tmp <= 23) {
281 get_time(NVRAM, &tm);
283 set_time(NVRAM, &tm);
287 /* day of the week / century */
288 tmp = fromBCD(val & 0x07);
289 get_time(NVRAM, &tm);
291 set_time(NVRAM, &tm);
292 NVRAM->buffer[0x1FFC] = val & 0x40;
296 tmp = fromBCD(val & 0x1F);
298 get_time(NVRAM, &tm);
300 set_time(NVRAM, &tm);
305 tmp = fromBCD(val & 0x1F);
306 if (tmp >= 1 && tmp <= 12) {
307 get_time(NVRAM, &tm);
309 set_time(NVRAM, &tm);
315 if (tmp >= 0 && tmp <= 99) {
316 get_time(NVRAM, &tm);
317 tm.tm_year = fromBCD(val);
318 set_time(NVRAM, &tm);
322 /* Check lock registers state */
323 if (NVRAM->addr >= 0x20 && NVRAM->addr <= 0x2F && (NVRAM->lock & 1))
325 if (NVRAM->addr >= 0x30 && NVRAM->addr <= 0x3F && (NVRAM->lock & 2))
327 if (NVRAM->addr < 0x1FF0 ||
328 (NVRAM->addr > 0x1FFF && NVRAM->addr < NVRAM->size)) {
329 NVRAM->buffer[NVRAM->addr] = val & 0xFF;
335 uint32_t m48t59_read (m48t59_t *NVRAM)
338 uint32_t retval = 0xFF;
340 switch (NVRAM->addr) {
364 /* A read resets the watchdog */
365 set_up_watchdog(NVRAM, NVRAM->buffer[0x1FF7]);
372 get_time(NVRAM, &tm);
373 retval = (NVRAM->buffer[0x1FF9] & 0x80) | toBCD(tm.tm_sec);
377 get_time(NVRAM, &tm);
378 retval = toBCD(tm.tm_min);
382 get_time(NVRAM, &tm);
383 retval = toBCD(tm.tm_hour);
386 /* day of the week / century */
387 get_time(NVRAM, &tm);
388 retval = NVRAM->buffer[0x1FFC] | tm.tm_wday;
392 get_time(NVRAM, &tm);
393 retval = toBCD(tm.tm_mday);
397 get_time(NVRAM, &tm);
398 retval = toBCD(tm.tm_mon + 1);
402 get_time(NVRAM, &tm);
403 retval = toBCD(tm.tm_year);
406 /* Check lock registers state */
407 if (NVRAM->addr >= 0x20 && NVRAM->addr <= 0x2F && (NVRAM->lock & 1))
409 if (NVRAM->addr >= 0x30 && NVRAM->addr <= 0x3F && (NVRAM->lock & 2))
411 if (NVRAM->addr < 0x1FF0 ||
412 (NVRAM->addr > 0x1FFF && NVRAM->addr < NVRAM->size)) {
414 retval = NVRAM->buffer[NVRAM->addr];
418 if (NVRAM->addr > 0x1FF9 && NVRAM->addr < 0x2000)
419 NVRAM_PRINTF("0x%08x <= 0x%08x\n", NVRAM->addr, retval);
424 void m48t59_set_addr (m48t59_t *NVRAM, uint32_t addr)
429 void m48t59_toggle_lock (m48t59_t *NVRAM, int lock)
431 NVRAM->lock ^= 1 << lock;
434 /* IO access to NVRAM */
435 static void NVRAM_writeb (void *opaque, uint32_t addr, uint32_t val)
437 m48t59_t *NVRAM = opaque;
439 addr -= NVRAM->io_base;
440 NVRAM_PRINTF("0x%08x => 0x%08x\n", addr, val);
443 NVRAM->addr &= ~0x00FF;
447 NVRAM->addr &= ~0xFF00;
448 NVRAM->addr |= val << 8;
451 m48t59_write(NVRAM, val);
452 NVRAM->addr = 0x0000;
459 static uint32_t NVRAM_readb (void *opaque, uint32_t addr)
461 m48t59_t *NVRAM = opaque;
464 addr -= NVRAM->io_base;
467 retval = m48t59_read(NVRAM);
473 NVRAM_PRINTF("0x%08x <= 0x%08x\n", addr, retval);
478 /* Initialisation routine */
479 m48t59_t *m48t59_init (int IRQ, uint32_t io_base, uint16_t size)
483 s = qemu_mallocz(sizeof(m48t59_t));
486 s->buffer = qemu_mallocz(size);
493 s->io_base = io_base;
495 register_ioport_read(io_base, 0x04, 1, NVRAM_readb, s);
496 register_ioport_write(io_base, 0x04, 1, NVRAM_writeb, s);
497 s->alrm_timer = qemu_new_timer(vm_clock, &alarm_cb, s);
498 s->wd_timer = qemu_new_timer(vm_clock, &watchdog_cb, s);