4 * Copyright (c) 2003-2004 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 /* debug LANCE card */
29 #define PHYS_JJ_IOMMU 0x10000000 /* First page of sun4m IOMMU */
30 #define PHYS_JJ_LEDMA 0x78400010 /* ledma, off by 10 from unused SCSI */
31 #define PHYS_JJ_LE 0x78C00000 /* LANCE, typical sun4m */
33 #ifndef LANCE_LOG_TX_BUFFERS
34 #define LANCE_LOG_TX_BUFFERS 4
35 #define LANCE_LOG_RX_BUFFERS 4
38 #define CRC_POLYNOMIAL_BE 0x04c11db7UL /* Ethernet CRC, big endian */
39 #define CRC_POLYNOMIAL_LE 0xedb88320UL /* Ethernet CRC, little endian */
46 #define LE_MAXREG (LE_CSR3 + 1)
51 #define LE_MO_PROM 0x8000 /* Enable promiscuous mode */
53 #define LE_C0_ERR 0x8000 /* Error: set if BAB, SQE, MISS or ME is set */
54 #define LE_C0_BABL 0x4000 /* BAB: Babble: tx timeout. */
55 #define LE_C0_CERR 0x2000 /* SQE: Signal quality error */
56 #define LE_C0_MISS 0x1000 /* MISS: Missed a packet */
57 #define LE_C0_MERR 0x0800 /* ME: Memory error */
58 #define LE_C0_RINT 0x0400 /* Received interrupt */
59 #define LE_C0_TINT 0x0200 /* Transmitter Interrupt */
60 #define LE_C0_IDON 0x0100 /* IFIN: Init finished. */
61 #define LE_C0_INTR 0x0080 /* Interrupt or error */
62 #define LE_C0_INEA 0x0040 /* Interrupt enable */
63 #define LE_C0_RXON 0x0020 /* Receiver on */
64 #define LE_C0_TXON 0x0010 /* Transmitter on */
65 #define LE_C0_TDMD 0x0008 /* Transmitter demand */
66 #define LE_C0_STOP 0x0004 /* Stop the card */
67 #define LE_C0_STRT 0x0002 /* Start the card */
68 #define LE_C0_INIT 0x0001 /* Init the card */
70 #define LE_C3_BSWP 0x4 /* SWAP */
71 #define LE_C3_ACON 0x2 /* ALE Control */
72 #define LE_C3_BCON 0x1 /* Byte control */
74 /* Receive message descriptor 1 */
75 #define LE_R1_OWN 0x80 /* Who owns the entry */
76 #define LE_R1_ERR 0x40 /* Error: if FRA, OFL, CRC or BUF is set */
77 #define LE_R1_FRA 0x20 /* FRA: Frame error */
78 #define LE_R1_OFL 0x10 /* OFL: Frame overflow */
79 #define LE_R1_CRC 0x08 /* CRC error */
80 #define LE_R1_BUF 0x04 /* BUF: Buffer error */
81 #define LE_R1_SOP 0x02 /* Start of packet */
82 #define LE_R1_EOP 0x01 /* End of packet */
83 #define LE_R1_POK 0x03 /* Packet is complete: SOP + EOP */
85 #define LE_T1_OWN 0x80 /* Lance owns the packet */
86 #define LE_T1_ERR 0x40 /* Error summary */
87 #define LE_T1_EMORE 0x10 /* Error: more than one retry needed */
88 #define LE_T1_EONE 0x08 /* Error: one retry needed */
89 #define LE_T1_EDEF 0x04 /* Error: deferred */
90 #define LE_T1_SOP 0x02 /* Start of packet */
91 #define LE_T1_EOP 0x01 /* End of packet */
92 #define LE_T1_POK 0x03 /* Packet is complete: SOP + EOP */
94 #define LE_T3_BUF 0x8000 /* Buffer error */
95 #define LE_T3_UFL 0x4000 /* Error underflow */
96 #define LE_T3_LCOL 0x1000 /* Error late collision */
97 #define LE_T3_CLOS 0x0800 /* Error carrier loss */
98 #define LE_T3_RTY 0x0400 /* Error retry */
99 #define LE_T3_TDR 0x03ff /* Time Domain Reflectometry counter */
101 #define TX_RING_SIZE (1 << (LANCE_LOG_TX_BUFFERS))
102 #define TX_RING_MOD_MASK (TX_RING_SIZE - 1)
103 #define TX_RING_LEN_BITS ((LANCE_LOG_TX_BUFFERS) << 29)
105 #define RX_RING_SIZE (1 << (LANCE_LOG_RX_BUFFERS))
106 #define RX_RING_MOD_MASK (RX_RING_SIZE - 1)
107 #define RX_RING_LEN_BITS ((LANCE_LOG_RX_BUFFERS) << 29)
109 #define PKT_BUF_SZ 1544
110 #define RX_BUFF_SIZE PKT_BUF_SZ
111 #define TX_BUFF_SIZE PKT_BUF_SZ
113 struct lance_rx_desc {
114 unsigned short rmd0; /* low address of packet */
115 unsigned char rmd1_bits; /* descriptor bits */
116 unsigned char rmd1_hadr; /* high address of packet */
117 short length; /* This length is 2s complement (negative)!
120 unsigned short mblength; /* This is the actual number of bytes received */
123 struct lance_tx_desc {
124 unsigned short tmd0; /* low address of packet */
125 unsigned char tmd1_bits; /* descriptor bits */
126 unsigned char tmd1_hadr; /* high address of packet */
127 short length; /* Length is 2s complement (negative)! */
131 /* The LANCE initialization block, described in databook. */
132 /* On the Sparc, this block should be on a DMA region */
133 struct lance_init_block {
134 unsigned short mode; /* Pre-set mode (reg. 15) */
135 unsigned char phys_addr[6]; /* Physical ethernet address */
136 unsigned filter[2]; /* Multicast filter. */
138 /* Receive and transmit ring base, along with extra bits. */
139 unsigned short rx_ptr; /* receive descriptor addr */
140 unsigned short rx_len; /* receive len and high addr */
141 unsigned short tx_ptr; /* transmit descriptor addr */
142 unsigned short tx_len; /* transmit len and high addr */
144 /* The Tx and Rx ring entries must aligned on 8-byte boundaries. */
145 struct lance_rx_desc brx_ring[RX_RING_SIZE];
146 struct lance_tx_desc btx_ring[TX_RING_SIZE];
148 char tx_buf [TX_RING_SIZE][TX_BUFF_SIZE];
149 char pad[2]; /* align rx_buf for copy_and_sum(). */
150 char rx_buf [RX_RING_SIZE][RX_BUFF_SIZE];
155 /* Structure to describe the current status of DMA registers on the Sparc */
156 struct sparc_dma_registers {
157 uint32_t cond_reg; /* DMA condition register */
158 uint32_t st_addr; /* Start address of this transfer */
159 uint32_t cnt; /* How many bytes to transfer */
160 uint32_t dma_test; /* DMA test register */
164 typedef struct LEDMAState {
165 uint32_t regs[LEDMA_REGS];
168 typedef struct LANCEState {
172 uint16_t regs[LE_MAXREG];
173 uint8_t phys[6]; /* mac address */
178 static int lance_io_memory;
180 static unsigned int rxptr, txptr;
182 static void lance_send(void *opaque);
184 static void lance_reset(LANCEState *s)
186 memcpy(s->phys, s->nd->macaddr, 6);
189 s->regs[LE_CSR0] = LE_C0_STOP;
192 static uint32_t lance_mem_readw(void *opaque, target_phys_addr_t addr)
194 LANCEState *s = opaque;
197 saddr = addr - PHYS_JJ_LE;
198 switch (saddr >> 1) {
200 return s->regs[s->addr];
209 static void lance_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
211 LANCEState *s = opaque;
215 saddr = addr - PHYS_JJ_LE;
216 switch (saddr >> 1) {
220 if (val & LE_C0_STOP) {
221 s->regs[LE_CSR0] = LE_C0_STOP;
225 reg = s->regs[LE_CSR0];
227 // 1 = clear for some bits
228 reg &= ~(val & 0x7f00);
231 reg &= ~(LE_C0_ERR | LE_C0_INTR);
239 reg |= val & LE_C0_INEA;
242 if (val & LE_C0_INIT) {
243 reg |= LE_C0_IDON | LE_C0_INIT;
246 else if (val & LE_C0_STRT) {
247 reg |= LE_C0_STRT | LE_C0_RXON | LE_C0_TXON;
251 s->regs[LE_CSR0] = reg;
254 //if (val & LE_C0_TDMD)
256 if ((s->regs[LE_CSR0] & LE_C0_INTR) && (s->regs[LE_CSR0] & LE_C0_INEA))
257 pic_set_irq(s->irq, 1);
260 s->leptr = (s->leptr & 0xffff0000) | (val & 0xffff);
261 s->regs[s->addr] = val;
264 s->leptr = (s->leptr & 0xffff) | ((val & 0xffff) << 16);
265 s->regs[s->addr] = val;
268 s->regs[s->addr] = val;
282 static CPUReadMemoryFunc *lance_mem_read[3] = {
288 static CPUWriteMemoryFunc *lance_mem_write[3] = {
295 /* return the max buffer size if the LANCE can receive more data */
296 static int lance_can_receive(void *opaque)
298 LANCEState *s = opaque;
299 void *dmaptr = (void *) (s->leptr + s->ledma->regs[3]);
300 struct lance_init_block *ib;
304 if ((s->regs[LE_CSR0] & LE_C0_STOP) == LE_C0_STOP)
307 ib = (void *) iommu_translate(dmaptr);
309 for (i = 0; i < RX_RING_SIZE; i++) {
310 cpu_physical_memory_read(&ib->brx_ring[i].rmd1_bits, (void *) &temp, 1);
312 if (temp == (LE_R1_OWN)) {
314 fprintf(stderr, "lance: can receive %d\n", RX_BUFF_SIZE);
320 fprintf(stderr, "lance: cannot receive\n");
325 #define MIN_BUF_SIZE 60
327 static void lance_receive(void *opaque, const uint8_t *buf, int size)
329 LANCEState *s = opaque;
330 void *dmaptr = (void *) (s->leptr + s->ledma->regs[3]);
331 struct lance_init_block *ib;
332 unsigned int i, old_rxptr, j;
335 if ((s->regs[LE_CSR0] & LE_C0_STOP) == LE_C0_STOP)
338 ib = (void *) iommu_translate(dmaptr);
341 for (i = rxptr; i != ((old_rxptr - 1) & RX_RING_MOD_MASK); i = (i + 1) & RX_RING_MOD_MASK) {
342 cpu_physical_memory_read(&ib->brx_ring[i].rmd1_bits, (void *) &temp, 1);
343 if (temp == (LE_R1_OWN)) {
344 rxptr = (rxptr + 1) & RX_RING_MOD_MASK;
347 cpu_physical_memory_write(&ib->brx_ring[i].mblength, (void *) &temp, 2);
349 cpu_physical_memory_write(&ib->rx_buf[i], buf, size);
351 for (j = 0; j < size; j++) {
352 cpu_physical_memory_write(((void *)&ib->rx_buf[i]) + j, &buf[j], 1);
356 cpu_physical_memory_write(&ib->brx_ring[i].rmd1_bits, (void *) &temp, 1);
357 s->regs[LE_CSR0] |= LE_C0_RINT | LE_C0_INTR;
358 if ((s->regs[LE_CSR0] & LE_C0_INTR) && (s->regs[LE_CSR0] & LE_C0_INEA))
359 pic_set_irq(s->irq, 1);
361 fprintf(stderr, "lance: got packet, len %d\n", size);
368 static void lance_send(void *opaque)
370 LANCEState *s = opaque;
371 void *dmaptr = (void *) (s->leptr + s->ledma->regs[3]);
372 struct lance_init_block *ib;
373 unsigned int i, old_txptr, j;
375 char pkt_buf[PKT_BUF_SZ];
377 if ((s->regs[LE_CSR0] & LE_C0_STOP) == LE_C0_STOP)
380 ib = (void *) iommu_translate(dmaptr);
383 for (i = txptr; i != ((old_txptr - 1) & TX_RING_MOD_MASK); i = (i + 1) & TX_RING_MOD_MASK) {
384 cpu_physical_memory_read(&ib->btx_ring[i].tmd1_bits, (void *) &temp, 1);
385 if (temp == (LE_T1_POK|LE_T1_OWN)) {
386 cpu_physical_memory_read(&ib->btx_ring[i].length, (void *) &temp, 2);
390 cpu_physical_memory_read(&ib->tx_buf[i], pkt_buf, temp);
392 for (j = 0; j < temp; j++) {
393 cpu_physical_memory_read(((void *)&ib->tx_buf[i]) + j, &pkt_buf[j], 1);
398 fprintf(stderr, "lance: sending packet, len %d\n", temp);
400 qemu_send_packet(s->nd, pkt_buf, temp);
402 cpu_physical_memory_write(&ib->btx_ring[i].tmd1_bits, (void *) &temp, 1);
403 txptr = (txptr + 1) & TX_RING_MOD_MASK;
404 s->regs[LE_CSR0] |= LE_C0_TINT | LE_C0_INTR;
409 static int ledma_io_memory;
411 static uint32_t ledma_mem_readl(void *opaque, target_phys_addr_t addr)
413 LEDMAState *s = opaque;
416 saddr = (addr - PHYS_JJ_LEDMA) >> 2;
417 if (saddr < LEDMA_REGS)
418 return s->regs[saddr];
423 static void ledma_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
425 LEDMAState *s = opaque;
428 saddr = (addr - PHYS_JJ_LEDMA) >> 2;
429 if (saddr < LEDMA_REGS)
430 s->regs[saddr] = val;
433 static CPUReadMemoryFunc *ledma_mem_read[3] = {
439 static CPUWriteMemoryFunc *ledma_mem_write[3] = {
445 void lance_init(NetDriverState *nd, int irq)
450 s = qemu_mallocz(sizeof(LANCEState));
454 lance_io_memory = cpu_register_io_memory(0, lance_mem_read, lance_mem_write, s);
455 cpu_register_physical_memory(PHYS_JJ_LE, 8,
457 led = qemu_mallocz(sizeof(LEDMAState));
461 ledma_io_memory = cpu_register_io_memory(0, ledma_mem_read, ledma_mem_write, led);
462 cpu_register_physical_memory(PHYS_JJ_LEDMA, 16,
470 qemu_add_read_packet(nd, lance_can_receive, lance_receive, s);