2 * QEMU 8259 interrupt controller emulation
4 * Copyright (c) 2003-2004 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
41 #include <netinet/in.h>
49 //#define DEBUG_IRQ_LATENCY
51 typedef struct PicState {
52 uint8_t last_irr; /* edge detection */
53 uint8_t irr; /* interrupt request register */
54 uint8_t imr; /* interrupt mask register */
55 uint8_t isr; /* interrupt service register */
56 uint8_t priority_add; /* highest irq priority */
58 uint8_t read_reg_select;
63 uint8_t rotate_on_auto_eoi;
64 uint8_t special_fully_nested_mode;
65 uint8_t init4; /* true if 4 byte init */
68 /* 0 is master pic, 1 is slave pic */
70 int pic_irq_requested;
72 /* set irq level. If an edge is detected, then the IRR is set to 1 */
73 static inline void pic_set_irq1(PicState *s, int irq, int level)
78 if ((s->last_irr & mask) == 0)
86 /* return the highest priority found in mask (highest = smallest
87 number). Return 8 if no irq */
88 static inline int get_priority(PicState *s, int mask)
94 while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0)
99 /* return the pic wanted interrupt. return -1 if none */
100 static int pic_get_irq(PicState *s)
102 int mask, cur_priority, priority;
104 mask = s->irr & ~s->imr;
105 priority = get_priority(s, mask);
108 /* compute current priority. If special fully nested mode on the
109 master, the IRQ coming from the slave is not taken into account
110 for the priority computation. */
112 if (s->special_fully_nested_mode && s == &pics[0])
114 cur_priority = get_priority(s, mask);
115 if (priority < cur_priority) {
116 /* higher priority found: an irq should be generated */
117 return (priority + s->priority_add) & 7;
123 /* raise irq to CPU if necessary. must be called every time the active
125 static void pic_update_irq(void)
129 /* first look at slave pic */
130 irq2 = pic_get_irq(&pics[1]);
132 /* if irq request by slave pic, signal master PIC */
133 pic_set_irq1(&pics[0], 2, 1);
134 pic_set_irq1(&pics[0], 2, 0);
136 /* look at requested irq */
137 irq = pic_get_irq(&pics[0]);
141 pic_irq_requested = 8 + irq2;
143 /* from master pic */
144 pic_irq_requested = irq;
146 #if defined(DEBUG_PIC)
149 for(i = 0; i < 2; i++) {
150 printf("pic%d: imr=%x irr=%x padd=%d\n",
151 i, pics[i].imr, pics[i].irr, pics[i].priority_add);
155 printf("pic: cpu_interrupt req=%d\n", pic_irq_requested);
157 cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HARD);
161 #ifdef DEBUG_IRQ_LATENCY
162 int64_t irq_time[16];
164 #if defined(DEBUG_PIC)
168 void pic_set_irq(int irq, int level)
170 #if defined(DEBUG_PIC)
171 if (level != irq_level[irq]) {
172 printf("pic_set_irq: irq=%d level=%d\n", irq, level);
173 irq_level[irq] = level;
176 #ifdef DEBUG_IRQ_LATENCY
178 irq_time[irq] = cpu_get_ticks();
181 pic_set_irq1(&pics[irq >> 3], irq & 7, level);
185 /* acknowledge interrupt 'irq' */
186 static inline void pic_intack(PicState *s, int irq)
189 if (s->rotate_on_auto_eoi)
190 s->priority_add = (irq + 1) & 7;
192 s->isr |= (1 << irq);
194 s->irr &= ~(1 << irq);
197 int cpu_x86_get_pic_interrupt(CPUState *env)
199 int irq, irq2, intno;
201 /* signal the pic that the irq was acked by the CPU */
202 irq = pic_irq_requested;
203 #ifdef DEBUG_IRQ_LATENCY
204 printf("IRQ%d latency=%0.3fus\n",
206 (double)(cpu_get_ticks() - irq_time[irq]) * 1000000.0 / ticks_per_sec);
208 #if defined(DEBUG_PIC)
209 printf("pic_interrupt: irq=%d\n", irq);
214 pic_intack(&pics[1], irq2);
216 intno = pics[1].irq_base + irq2;
218 intno = pics[0].irq_base + irq;
220 pic_intack(&pics[0], irq);
224 static void pic_ioport_write(void *opaque, uint32_t addr, uint32_t val)
226 PicState *s = opaque;
227 int priority, cmd, irq;
230 printf("pic_write: addr=0x%02x val=0x%02x\n", addr, val);
236 memset(s, 0, sizeof(PicState));
240 hw_error("single mode not supported");
242 hw_error("level sensitive irq not supported");
243 } else if (val & 0x08) {
247 s->read_reg_select = val & 1;
249 s->special_mask = (val >> 5) & 1;
255 s->rotate_on_auto_eoi = cmd >> 2;
257 case 1: /* end of interrupt */
259 priority = get_priority(s, s->isr);
261 irq = (priority + s->priority_add) & 7;
262 s->isr &= ~(1 << irq);
264 s->priority_add = (irq + 1) & 7;
270 s->isr &= ~(1 << irq);
274 s->priority_add = (val + 1) & 7;
279 s->isr &= ~(1 << irq);
280 s->priority_add = (irq + 1) & 7;
289 switch(s->init_state) {
296 s->irq_base = val & 0xf8;
307 s->special_fully_nested_mode = (val >> 4) & 1;
308 s->auto_eoi = (val >> 1) & 1;
315 static uint32_t pic_poll_read (PicState *s, uint32_t addr1)
319 ret = pic_get_irq(s);
322 pics[0].isr &= ~(1 << 2);
323 pics[0].irr &= ~(1 << 2);
325 s->irr &= ~(1 << ret);
326 s->isr &= ~(1 << ret);
327 if (addr1 >> 7 || ret != 2)
337 static uint32_t pic_ioport_read(void *opaque, uint32_t addr1)
339 PicState *s = opaque;
346 ret = pic_poll_read(s, addr1);
350 if (s->read_reg_select)
359 printf("pic_read: addr=0x%02x val=0x%02x\n", addr1, ret);
364 /* memory mapped interrupt status */
365 uint32_t pic_intack_read(CPUState *env)
369 ret = pic_poll_read(&pics[0], 0x00);
371 ret = pic_poll_read(&pics[1], 0x80) + 8;
372 /* Prepare for ISR read */
373 pics[0].read_reg_select = 1;
378 static void pic_save(QEMUFile *f, void *opaque)
380 PicState *s = opaque;
382 qemu_put_8s(f, &s->last_irr);
383 qemu_put_8s(f, &s->irr);
384 qemu_put_8s(f, &s->imr);
385 qemu_put_8s(f, &s->isr);
386 qemu_put_8s(f, &s->priority_add);
387 qemu_put_8s(f, &s->irq_base);
388 qemu_put_8s(f, &s->read_reg_select);
389 qemu_put_8s(f, &s->poll);
390 qemu_put_8s(f, &s->special_mask);
391 qemu_put_8s(f, &s->init_state);
392 qemu_put_8s(f, &s->auto_eoi);
393 qemu_put_8s(f, &s->rotate_on_auto_eoi);
394 qemu_put_8s(f, &s->special_fully_nested_mode);
395 qemu_put_8s(f, &s->init4);
398 static int pic_load(QEMUFile *f, void *opaque, int version_id)
400 PicState *s = opaque;
405 qemu_get_8s(f, &s->last_irr);
406 qemu_get_8s(f, &s->irr);
407 qemu_get_8s(f, &s->imr);
408 qemu_get_8s(f, &s->isr);
409 qemu_get_8s(f, &s->priority_add);
410 qemu_get_8s(f, &s->irq_base);
411 qemu_get_8s(f, &s->read_reg_select);
412 qemu_get_8s(f, &s->poll);
413 qemu_get_8s(f, &s->special_mask);
414 qemu_get_8s(f, &s->init_state);
415 qemu_get_8s(f, &s->auto_eoi);
416 qemu_get_8s(f, &s->rotate_on_auto_eoi);
417 qemu_get_8s(f, &s->special_fully_nested_mode);
418 qemu_get_8s(f, &s->init4);
422 /* XXX: add generic master/slave system */
423 static void pic_init1(int io_addr, PicState *s)
425 register_ioport_write(io_addr, 2, 1, pic_ioport_write, s);
426 register_ioport_read(io_addr, 2, 1, pic_ioport_read, s);
428 register_savevm("i8259", io_addr, 1, pic_save, pic_load, s);
433 pic_init1(0x20, &pics[0]);
434 pic_init1(0xa0, &pics[1]);