2 * QEMU 8259 interrupt controller emulation
4 * Copyright (c) 2003-2004 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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41 #include <netinet/in.h>
49 typedef struct PicState {
50 uint8_t last_irr; /* edge detection */
51 uint8_t irr; /* interrupt request register */
52 uint8_t imr; /* interrupt mask register */
53 uint8_t isr; /* interrupt service register */
54 uint8_t priority_add; /* highest irq priority */
56 uint8_t read_reg_select;
61 uint8_t rotate_on_auto_eoi;
62 uint8_t special_fully_nested_mode;
63 uint8_t init4; /* true if 4 byte init */
66 /* 0 is master pic, 1 is slave pic */
68 int pic_irq_requested;
70 /* set irq level. If an edge is detected, then the IRR is set to 1 */
71 static inline void pic_set_irq1(PicState *s, int irq, int level)
76 if ((s->last_irr & mask) == 0)
84 /* return the highest priority found in mask (highest = smallest
85 number). Return 8 if no irq */
86 static inline int get_priority(PicState *s, int mask)
92 while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0)
97 /* return the pic wanted interrupt. return -1 if none */
98 static int pic_get_irq(PicState *s)
100 int mask, cur_priority, priority;
102 mask = s->irr & ~s->imr;
103 priority = get_priority(s, mask);
106 /* compute current priority. If special fully nested mode on the
107 master, the IRQ coming from the slave is not taken into account
108 for the priority computation. */
110 if (s->special_fully_nested_mode && s == &pics[0])
112 cur_priority = get_priority(s, mask);
113 if (priority < cur_priority) {
114 /* higher priority found: an irq should be generated */
115 return (priority + s->priority_add) & 7;
121 /* raise irq to CPU if necessary. must be called every time the active
123 void pic_update_irq(void)
127 /* first look at slave pic */
128 irq2 = pic_get_irq(&pics[1]);
130 /* if irq request by slave pic, signal master PIC */
131 pic_set_irq1(&pics[0], 2, 1);
132 pic_set_irq1(&pics[0], 2, 0);
134 /* look at requested irq */
135 irq = pic_get_irq(&pics[0]);
139 pic_irq_requested = 8 + irq2;
141 /* from master pic */
142 pic_irq_requested = irq;
144 #if defined(DEBUG_PIC)
147 for(i = 0; i < 2; i++) {
148 printf("pic%d: imr=%x irr=%x padd=%d\n",
149 i, pics[i].imr, pics[i].irr, pics[i].priority_add);
153 printf("pic: cpu_interrupt req=%d\n", pic_irq_requested);
155 cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HARD);
159 #ifdef DEBUG_IRQ_LATENCY
160 int64_t irq_time[16];
161 int64_t cpu_get_ticks(void);
163 #if defined(DEBUG_PIC)
167 void pic_set_irq(int irq, int level)
169 #if defined(DEBUG_PIC)
170 if (level != irq_level[irq]) {
171 printf("pic_set_irq: irq=%d level=%d\n", irq, level);
172 irq_level[irq] = level;
175 #ifdef DEBUG_IRQ_LATENCY
177 irq_time[irq] = cpu_get_ticks();
180 pic_set_irq1(&pics[irq >> 3], irq & 7, level);
184 /* acknowledge interrupt 'irq' */
185 static inline void pic_intack(PicState *s, int irq)
188 if (s->rotate_on_auto_eoi)
189 s->priority_add = (irq + 1) & 7;
191 s->isr |= (1 << irq);
193 s->irr &= ~(1 << irq);
196 int cpu_x86_get_pic_interrupt(CPUState *env)
198 int irq, irq2, intno;
200 /* signal the pic that the irq was acked by the CPU */
201 irq = pic_irq_requested;
202 #ifdef DEBUG_IRQ_LATENCY
203 printf("IRQ%d latency=%0.3fus\n",
205 (double)(cpu_get_ticks() - irq_time[irq]) * 1000000.0 / ticks_per_sec);
207 #if defined(DEBUG_PIC)
208 printf("pic_interrupt: irq=%d\n", irq);
213 pic_intack(&pics[1], irq2);
215 intno = pics[1].irq_base + irq2;
217 intno = pics[0].irq_base + irq;
219 pic_intack(&pics[0], irq);
223 void pic_ioport_write(CPUState *env, uint32_t addr, uint32_t val)
226 int priority, cmd, irq;
229 printf("pic_write: addr=0x%02x val=0x%02x\n", addr, val);
231 s = &pics[addr >> 7];
236 memset(s, 0, sizeof(PicState));
240 hw_error("single mode not supported");
242 hw_error("level sensitive irq not supported");
243 } else if (val & 0x08) {
247 s->read_reg_select = val & 1;
249 s->special_mask = (val >> 5) & 1;
255 s->rotate_on_auto_eoi = cmd >> 2;
257 case 1: /* end of interrupt */
259 priority = get_priority(s, s->isr);
261 irq = (priority + s->priority_add) & 7;
262 s->isr &= ~(1 << irq);
264 s->priority_add = (irq + 1) & 7;
270 s->isr &= ~(1 << irq);
274 s->priority_add = (val + 1) & 7;
279 s->isr &= ~(1 << irq);
280 s->priority_add = (irq + 1) & 7;
289 switch(s->init_state) {
296 s->irq_base = val & 0xf8;
307 s->special_fully_nested_mode = (val >> 4) & 1;
308 s->auto_eoi = (val >> 1) & 1;
315 static uint32_t pic_poll_read (PicState *s, uint32_t addr1)
319 ret = pic_get_irq(s);
322 pics[0].isr &= ~(1 << 2);
323 pics[0].irr &= ~(1 << 2);
325 s->irr &= ~(1 << ret);
326 s->isr &= ~(1 << ret);
327 if (addr1 >> 7 || ret != 2)
337 uint32_t pic_ioport_read(CPUState *env, uint32_t addr1)
344 s = &pics[addr >> 7];
347 ret = pic_poll_read(s, addr1);
351 if (s->read_reg_select)
360 printf("pic_read: addr=0x%02x val=0x%02x\n", addr1, ret);
365 /* memory mapped interrupt status */
366 uint32_t pic_intack_read(CPUState *env)
370 ret = pic_poll_read(&pics[0], 0x00);
372 ret = pic_poll_read(&pics[1], 0x80) + 8;
373 /* Prepare for ISR read */
374 pics[0].read_reg_select = 1;
381 #if defined (TARGET_I386) || defined (TARGET_PPC)
382 register_ioport_write(0x20, 2, pic_ioport_write, 1);
383 register_ioport_read(0x20, 2, pic_ioport_read, 1);
384 register_ioport_write(0xa0, 2, pic_ioport_write, 1);
385 register_ioport_read(0xa0, 2, pic_ioport_read, 1);