2 * QEMU 8259 interrupt controller emulation
4 * Copyright (c) 2003-2004 Fabrice Bellard
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29 //#define DEBUG_IRQ_LATENCY
30 //#define DEBUG_IRQ_COUNT
32 typedef struct PicState {
33 uint8_t last_irr; /* edge detection */
34 uint8_t irr; /* interrupt request register */
35 uint8_t imr; /* interrupt mask register */
36 uint8_t isr; /* interrupt service register */
37 uint8_t priority_add; /* highest irq priority */
39 uint8_t read_reg_select;
44 uint8_t rotate_on_auto_eoi;
45 uint8_t special_fully_nested_mode;
46 uint8_t init4; /* true if 4 byte init */
47 uint8_t elcr; /* PIIX edge/trigger selection*/
49 PicState2 *pics_state;
53 /* 0 is master pic, 1 is slave pic */
54 /* XXX: better separation between the two pics */
56 IRQRequestFunc *irq_request;
57 void *irq_request_opaque;
60 #if defined(DEBUG_PIC) || defined (DEBUG_IRQ_COUNT)
61 static int irq_level[16];
63 #ifdef DEBUG_IRQ_COUNT
64 static uint64_t irq_count[16];
67 /* set irq level. If an edge is detected, then the IRR is set to 1 */
68 static inline void pic_set_irq1(PicState *s, int irq, int level)
84 if ((s->last_irr & mask) == 0)
93 /* return the highest priority found in mask (highest = smallest
94 number). Return 8 if no irq */
95 static inline int get_priority(PicState *s, int mask)
101 while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0)
106 /* return the pic wanted interrupt. return -1 if none */
107 static int pic_get_irq(PicState *s)
109 int mask, cur_priority, priority;
111 mask = s->irr & ~s->imr;
112 priority = get_priority(s, mask);
115 /* compute current priority. If special fully nested mode on the
116 master, the IRQ coming from the slave is not taken into account
117 for the priority computation. */
119 if (s->special_fully_nested_mode && s == &s->pics_state->pics[0])
121 cur_priority = get_priority(s, mask);
122 if (priority < cur_priority) {
123 /* higher priority found: an irq should be generated */
124 return (priority + s->priority_add) & 7;
130 /* raise irq to CPU if necessary. must be called every time the active
132 /* XXX: should not export it, but it is needed for an APIC kludge */
133 void pic_update_irq(PicState2 *s)
137 /* first look at slave pic */
138 irq2 = pic_get_irq(&s->pics[1]);
140 /* if irq request by slave pic, signal master PIC */
141 pic_set_irq1(&s->pics[0], 2, 1);
142 pic_set_irq1(&s->pics[0], 2, 0);
144 /* look at requested irq */
145 irq = pic_get_irq(&s->pics[0]);
147 #if defined(DEBUG_PIC)
150 for(i = 0; i < 2; i++) {
151 printf("pic%d: imr=%x irr=%x padd=%d\n",
152 i, s->pics[i].imr, s->pics[i].irr,
153 s->pics[i].priority_add);
157 printf("pic: cpu_interrupt\n");
159 s->irq_request(s->irq_request_opaque, 1);
163 #ifdef DEBUG_IRQ_LATENCY
164 int64_t irq_time[16];
167 void pic_set_irq_new(void *opaque, int irq, int level)
169 PicState2 *s = opaque;
171 #if defined(DEBUG_PIC) || defined(DEBUG_IRQ_COUNT)
172 if (level != irq_level[irq]) {
173 #if defined(DEBUG_PIC)
174 printf("pic_set_irq: irq=%d level=%d\n", irq, level);
176 irq_level[irq] = level;
177 #ifdef DEBUG_IRQ_COUNT
183 #ifdef DEBUG_IRQ_LATENCY
185 irq_time[irq] = qemu_get_clock(vm_clock);
188 pic_set_irq1(&s->pics[irq >> 3], irq & 7, level);
192 /* obsolete function */
193 void pic_set_irq(int irq, int level)
195 pic_set_irq_new(isa_pic, irq, level);
198 /* acknowledge interrupt 'irq' */
199 static inline void pic_intack(PicState *s, int irq)
202 if (s->rotate_on_auto_eoi)
203 s->priority_add = (irq + 1) & 7;
205 s->isr |= (1 << irq);
207 /* We don't clear a level sensitive interrupt here */
208 if (!(s->elcr & (1 << irq)))
209 s->irr &= ~(1 << irq);
212 int pic_read_irq(PicState2 *s)
214 int irq, irq2, intno;
216 irq = pic_get_irq(&s->pics[0]);
218 pic_intack(&s->pics[0], irq);
220 irq2 = pic_get_irq(&s->pics[1]);
222 pic_intack(&s->pics[1], irq2);
224 /* spurious IRQ on slave controller */
227 intno = s->pics[1].irq_base + irq2;
230 intno = s->pics[0].irq_base + irq;
233 /* spurious IRQ on host controller */
235 intno = s->pics[0].irq_base + irq;
239 #ifdef DEBUG_IRQ_LATENCY
240 printf("IRQ%d latency=%0.3fus\n",
242 (double)(qemu_get_clock(vm_clock) - irq_time[irq]) * 1000000.0 / ticks_per_sec);
244 #if defined(DEBUG_PIC)
245 printf("pic_interrupt: irq=%d\n", irq);
250 static void pic_reset(void *opaque)
252 PicState *s = opaque;
260 s->read_reg_select = 0;
265 s->rotate_on_auto_eoi = 0;
266 s->special_fully_nested_mode = 0;
271 static void pic_ioport_write(void *opaque, uint32_t addr, uint32_t val)
273 PicState *s = opaque;
274 int priority, cmd, irq;
277 printf("pic_write: addr=0x%02x val=0x%02x\n", addr, val);
284 /* deassert a pending interrupt */
285 s->pics_state->irq_request(s->pics_state->irq_request_opaque, 0);
289 hw_error("single mode not supported");
291 hw_error("level sensitive irq not supported");
292 } else if (val & 0x08) {
296 s->read_reg_select = val & 1;
298 s->special_mask = (val >> 5) & 1;
304 s->rotate_on_auto_eoi = cmd >> 2;
306 case 1: /* end of interrupt */
308 priority = get_priority(s, s->isr);
310 irq = (priority + s->priority_add) & 7;
311 s->isr &= ~(1 << irq);
313 s->priority_add = (irq + 1) & 7;
314 pic_update_irq(s->pics_state);
319 s->isr &= ~(1 << irq);
320 pic_update_irq(s->pics_state);
323 s->priority_add = (val + 1) & 7;
324 pic_update_irq(s->pics_state);
328 s->isr &= ~(1 << irq);
329 s->priority_add = (irq + 1) & 7;
330 pic_update_irq(s->pics_state);
338 switch(s->init_state) {
342 pic_update_irq(s->pics_state);
345 s->irq_base = val & 0xf8;
356 s->special_fully_nested_mode = (val >> 4) & 1;
357 s->auto_eoi = (val >> 1) & 1;
364 static uint32_t pic_poll_read (PicState *s, uint32_t addr1)
368 ret = pic_get_irq(s);
371 s->pics_state->pics[0].isr &= ~(1 << 2);
372 s->pics_state->pics[0].irr &= ~(1 << 2);
374 s->irr &= ~(1 << ret);
375 s->isr &= ~(1 << ret);
376 if (addr1 >> 7 || ret != 2)
377 pic_update_irq(s->pics_state);
380 pic_update_irq(s->pics_state);
386 static uint32_t pic_ioport_read(void *opaque, uint32_t addr1)
388 PicState *s = opaque;
395 ret = pic_poll_read(s, addr1);
399 if (s->read_reg_select)
408 printf("pic_read: addr=0x%02x val=0x%02x\n", addr1, ret);
413 /* memory mapped interrupt status */
414 /* XXX: may be the same than pic_read_irq() */
415 uint32_t pic_intack_read(PicState2 *s)
419 ret = pic_poll_read(&s->pics[0], 0x00);
421 ret = pic_poll_read(&s->pics[1], 0x80) + 8;
422 /* Prepare for ISR read */
423 s->pics[0].read_reg_select = 1;
428 static void elcr_ioport_write(void *opaque, uint32_t addr, uint32_t val)
430 PicState *s = opaque;
431 s->elcr = val & s->elcr_mask;
434 static uint32_t elcr_ioport_read(void *opaque, uint32_t addr1)
436 PicState *s = opaque;
440 static void pic_save(QEMUFile *f, void *opaque)
442 PicState *s = opaque;
444 qemu_put_8s(f, &s->last_irr);
445 qemu_put_8s(f, &s->irr);
446 qemu_put_8s(f, &s->imr);
447 qemu_put_8s(f, &s->isr);
448 qemu_put_8s(f, &s->priority_add);
449 qemu_put_8s(f, &s->irq_base);
450 qemu_put_8s(f, &s->read_reg_select);
451 qemu_put_8s(f, &s->poll);
452 qemu_put_8s(f, &s->special_mask);
453 qemu_put_8s(f, &s->init_state);
454 qemu_put_8s(f, &s->auto_eoi);
455 qemu_put_8s(f, &s->rotate_on_auto_eoi);
456 qemu_put_8s(f, &s->special_fully_nested_mode);
457 qemu_put_8s(f, &s->init4);
458 qemu_put_8s(f, &s->elcr);
461 static int pic_load(QEMUFile *f, void *opaque, int version_id)
463 PicState *s = opaque;
468 qemu_get_8s(f, &s->last_irr);
469 qemu_get_8s(f, &s->irr);
470 qemu_get_8s(f, &s->imr);
471 qemu_get_8s(f, &s->isr);
472 qemu_get_8s(f, &s->priority_add);
473 qemu_get_8s(f, &s->irq_base);
474 qemu_get_8s(f, &s->read_reg_select);
475 qemu_get_8s(f, &s->poll);
476 qemu_get_8s(f, &s->special_mask);
477 qemu_get_8s(f, &s->init_state);
478 qemu_get_8s(f, &s->auto_eoi);
479 qemu_get_8s(f, &s->rotate_on_auto_eoi);
480 qemu_get_8s(f, &s->special_fully_nested_mode);
481 qemu_get_8s(f, &s->init4);
482 qemu_get_8s(f, &s->elcr);
486 /* XXX: add generic master/slave system */
487 static void pic_init1(int io_addr, int elcr_addr, PicState *s)
489 register_ioport_write(io_addr, 2, 1, pic_ioport_write, s);
490 register_ioport_read(io_addr, 2, 1, pic_ioport_read, s);
491 if (elcr_addr >= 0) {
492 register_ioport_write(elcr_addr, 1, 1, elcr_ioport_write, s);
493 register_ioport_read(elcr_addr, 1, 1, elcr_ioport_read, s);
495 register_savevm("i8259", io_addr, 1, pic_save, pic_load, s);
496 qemu_register_reset(pic_reset, s);
508 s = &isa_pic->pics[i];
509 term_printf("pic%d: irr=%02x imr=%02x isr=%02x hprio=%d irq_base=%02x rr_sel=%d elcr=%02x fnm=%d\n",
510 i, s->irr, s->imr, s->isr, s->priority_add,
511 s->irq_base, s->read_reg_select, s->elcr,
512 s->special_fully_nested_mode);
518 #ifndef DEBUG_IRQ_COUNT
519 term_printf("irq statistic code not compiled.\n");
524 term_printf("IRQ statistics:\n");
525 for (i = 0; i < 16; i++) {
526 count = irq_count[i];
528 term_printf("%2d: %lld\n", i, count);
533 PicState2 *pic_init(IRQRequestFunc *irq_request, void *irq_request_opaque)
536 s = qemu_mallocz(sizeof(PicState2));
539 pic_init1(0x20, 0x4d0, &s->pics[0]);
540 pic_init1(0xa0, 0x4d1, &s->pics[1]);
541 s->pics[0].elcr_mask = 0xf8;
542 s->pics[1].elcr_mask = 0xde;
543 s->irq_request = irq_request;
544 s->irq_request_opaque = irq_request_opaque;
545 s->pics[0].pics_state = s;
546 s->pics[1].pics_state = s;