2 * QEMU 8259 interrupt controller emulation
4 * Copyright (c) 2003-2004 Fabrice Bellard
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29 //#define DEBUG_IRQ_LATENCY
30 //#define DEBUG_IRQ_COUNT
32 typedef struct PicState {
33 uint8_t last_irr; /* edge detection */
34 uint8_t irr; /* interrupt request register */
35 uint8_t imr; /* interrupt mask register */
36 uint8_t isr; /* interrupt service register */
37 uint8_t priority_add; /* highest irq priority */
39 uint8_t read_reg_select;
44 uint8_t rotate_on_auto_eoi;
45 uint8_t special_fully_nested_mode;
46 uint8_t init4; /* true if 4 byte init */
47 uint8_t single_mode; /* true if slave pic is not initialized */
48 uint8_t elcr; /* PIIX edge/trigger selection*/
50 PicState2 *pics_state;
54 /* 0 is master pic, 1 is slave pic */
55 /* XXX: better separation between the two pics */
57 IRQRequestFunc *irq_request;
58 void *irq_request_opaque;
59 /* IOAPIC callback support */
60 SetIRQFunc *alt_irq_func;
64 #if defined(DEBUG_PIC) || defined (DEBUG_IRQ_COUNT)
65 static int irq_level[16];
67 #ifdef DEBUG_IRQ_COUNT
68 static uint64_t irq_count[16];
71 /* set irq level. If an edge is detected, then the IRR is set to 1 */
72 static inline void pic_set_irq1(PicState *s, int irq, int level)
88 if ((s->last_irr & mask) == 0)
97 /* return the highest priority found in mask (highest = smallest
98 number). Return 8 if no irq */
99 static inline int get_priority(PicState *s, int mask)
105 while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0)
110 /* return the pic wanted interrupt. return -1 if none */
111 static int pic_get_irq(PicState *s)
113 int mask, cur_priority, priority;
115 mask = s->irr & ~s->imr;
116 priority = get_priority(s, mask);
119 /* compute current priority. If special fully nested mode on the
120 master, the IRQ coming from the slave is not taken into account
121 for the priority computation. */
123 if (s->special_fully_nested_mode && s == &s->pics_state->pics[0])
125 cur_priority = get_priority(s, mask);
126 if (priority < cur_priority) {
127 /* higher priority found: an irq should be generated */
128 return (priority + s->priority_add) & 7;
134 /* raise irq to CPU if necessary. must be called every time the active
136 /* XXX: should not export it, but it is needed for an APIC kludge */
137 void pic_update_irq(PicState2 *s)
141 /* first look at slave pic */
142 irq2 = pic_get_irq(&s->pics[1]);
144 /* if irq request by slave pic, signal master PIC */
145 pic_set_irq1(&s->pics[0], 2, 1);
146 pic_set_irq1(&s->pics[0], 2, 0);
148 /* look at requested irq */
149 irq = pic_get_irq(&s->pics[0]);
151 #if defined(DEBUG_PIC)
154 for(i = 0; i < 2; i++) {
155 printf("pic%d: imr=%x irr=%x padd=%d\n",
156 i, s->pics[i].imr, s->pics[i].irr,
157 s->pics[i].priority_add);
161 printf("pic: cpu_interrupt\n");
163 s->irq_request(s->irq_request_opaque, 1);
166 /* all targets should do this rather than acking the IRQ in the cpu */
167 #if defined(TARGET_MIPS)
169 s->irq_request(s->irq_request_opaque, 0);
174 #ifdef DEBUG_IRQ_LATENCY
175 int64_t irq_time[16];
178 void pic_set_irq_new(void *opaque, int irq, int level)
180 PicState2 *s = opaque;
182 #if defined(DEBUG_PIC) || defined(DEBUG_IRQ_COUNT)
183 if (level != irq_level[irq]) {
184 #if defined(DEBUG_PIC)
185 printf("pic_set_irq: irq=%d level=%d\n", irq, level);
187 irq_level[irq] = level;
188 #ifdef DEBUG_IRQ_COUNT
194 #ifdef DEBUG_IRQ_LATENCY
196 irq_time[irq] = qemu_get_clock(vm_clock);
199 pic_set_irq1(&s->pics[irq >> 3], irq & 7, level);
200 /* used for IOAPIC irqs */
202 s->alt_irq_func(s->alt_irq_opaque, irq, level);
206 /* obsolete function */
207 void pic_set_irq(int irq, int level)
209 pic_set_irq_new(isa_pic, irq, level);
212 /* acknowledge interrupt 'irq' */
213 static inline void pic_intack(PicState *s, int irq)
216 if (s->rotate_on_auto_eoi)
217 s->priority_add = (irq + 1) & 7;
219 s->isr |= (1 << irq);
221 /* We don't clear a level sensitive interrupt here */
222 if (!(s->elcr & (1 << irq)))
223 s->irr &= ~(1 << irq);
226 int pic_read_irq(PicState2 *s)
228 int irq, irq2, intno;
230 irq = pic_get_irq(&s->pics[0]);
232 pic_intack(&s->pics[0], irq);
234 irq2 = pic_get_irq(&s->pics[1]);
236 pic_intack(&s->pics[1], irq2);
238 /* spurious IRQ on slave controller */
241 intno = s->pics[1].irq_base + irq2;
244 intno = s->pics[0].irq_base + irq;
247 /* spurious IRQ on host controller */
249 intno = s->pics[0].irq_base + irq;
253 #ifdef DEBUG_IRQ_LATENCY
254 printf("IRQ%d latency=%0.3fus\n",
256 (double)(qemu_get_clock(vm_clock) - irq_time[irq]) * 1000000.0 / ticks_per_sec);
258 #if defined(DEBUG_PIC)
259 printf("pic_interrupt: irq=%d\n", irq);
264 static void pic_reset(void *opaque)
266 PicState *s = opaque;
274 s->read_reg_select = 0;
279 s->rotate_on_auto_eoi = 0;
280 s->special_fully_nested_mode = 0;
283 /* Note: ELCR is not reset */
286 static void pic_ioport_write(void *opaque, uint32_t addr, uint32_t val)
288 PicState *s = opaque;
289 int priority, cmd, irq;
292 printf("pic_write: addr=0x%02x val=0x%02x\n", addr, val);
299 /* deassert a pending interrupt */
300 s->pics_state->irq_request(s->pics_state->irq_request_opaque, 0);
303 s->single_mode = val & 2;
305 hw_error("level sensitive irq not supported");
306 } else if (val & 0x08) {
310 s->read_reg_select = val & 1;
312 s->special_mask = (val >> 5) & 1;
318 s->rotate_on_auto_eoi = cmd >> 2;
320 case 1: /* end of interrupt */
322 priority = get_priority(s, s->isr);
324 irq = (priority + s->priority_add) & 7;
325 s->isr &= ~(1 << irq);
327 s->priority_add = (irq + 1) & 7;
328 pic_update_irq(s->pics_state);
333 s->isr &= ~(1 << irq);
334 pic_update_irq(s->pics_state);
337 s->priority_add = (val + 1) & 7;
338 pic_update_irq(s->pics_state);
342 s->isr &= ~(1 << irq);
343 s->priority_add = (irq + 1) & 7;
344 pic_update_irq(s->pics_state);
352 switch(s->init_state) {
356 pic_update_irq(s->pics_state);
359 s->irq_base = val & 0xf8;
360 s->init_state = s->single_mode && s->init4 ? 3 : 2;
370 s->special_fully_nested_mode = (val >> 4) & 1;
371 s->auto_eoi = (val >> 1) & 1;
378 static uint32_t pic_poll_read (PicState *s, uint32_t addr1)
382 ret = pic_get_irq(s);
385 s->pics_state->pics[0].isr &= ~(1 << 2);
386 s->pics_state->pics[0].irr &= ~(1 << 2);
388 s->irr &= ~(1 << ret);
389 s->isr &= ~(1 << ret);
390 if (addr1 >> 7 || ret != 2)
391 pic_update_irq(s->pics_state);
394 pic_update_irq(s->pics_state);
400 static uint32_t pic_ioport_read(void *opaque, uint32_t addr1)
402 PicState *s = opaque;
409 ret = pic_poll_read(s, addr1);
413 if (s->read_reg_select)
422 printf("pic_read: addr=0x%02x val=0x%02x\n", addr1, ret);
427 /* memory mapped interrupt status */
428 /* XXX: may be the same than pic_read_irq() */
429 uint32_t pic_intack_read(PicState2 *s)
433 ret = pic_poll_read(&s->pics[0], 0x00);
435 ret = pic_poll_read(&s->pics[1], 0x80) + 8;
436 /* Prepare for ISR read */
437 s->pics[0].read_reg_select = 1;
442 static void elcr_ioport_write(void *opaque, uint32_t addr, uint32_t val)
444 PicState *s = opaque;
445 s->elcr = val & s->elcr_mask;
448 static uint32_t elcr_ioport_read(void *opaque, uint32_t addr1)
450 PicState *s = opaque;
454 static void pic_save(QEMUFile *f, void *opaque)
456 PicState *s = opaque;
458 qemu_put_8s(f, &s->last_irr);
459 qemu_put_8s(f, &s->irr);
460 qemu_put_8s(f, &s->imr);
461 qemu_put_8s(f, &s->isr);
462 qemu_put_8s(f, &s->priority_add);
463 qemu_put_8s(f, &s->irq_base);
464 qemu_put_8s(f, &s->read_reg_select);
465 qemu_put_8s(f, &s->poll);
466 qemu_put_8s(f, &s->special_mask);
467 qemu_put_8s(f, &s->init_state);
468 qemu_put_8s(f, &s->auto_eoi);
469 qemu_put_8s(f, &s->rotate_on_auto_eoi);
470 qemu_put_8s(f, &s->special_fully_nested_mode);
471 qemu_put_8s(f, &s->init4);
472 qemu_put_8s(f, &s->single_mode);
473 qemu_put_8s(f, &s->elcr);
476 static int pic_load(QEMUFile *f, void *opaque, int version_id)
478 PicState *s = opaque;
483 qemu_get_8s(f, &s->last_irr);
484 qemu_get_8s(f, &s->irr);
485 qemu_get_8s(f, &s->imr);
486 qemu_get_8s(f, &s->isr);
487 qemu_get_8s(f, &s->priority_add);
488 qemu_get_8s(f, &s->irq_base);
489 qemu_get_8s(f, &s->read_reg_select);
490 qemu_get_8s(f, &s->poll);
491 qemu_get_8s(f, &s->special_mask);
492 qemu_get_8s(f, &s->init_state);
493 qemu_get_8s(f, &s->auto_eoi);
494 qemu_get_8s(f, &s->rotate_on_auto_eoi);
495 qemu_get_8s(f, &s->special_fully_nested_mode);
496 qemu_get_8s(f, &s->init4);
497 qemu_get_8s(f, &s->single_mode);
498 qemu_get_8s(f, &s->elcr);
502 /* XXX: add generic master/slave system */
503 static void pic_init1(int io_addr, int elcr_addr, PicState *s)
505 register_ioport_write(io_addr, 2, 1, pic_ioport_write, s);
506 register_ioport_read(io_addr, 2, 1, pic_ioport_read, s);
507 if (elcr_addr >= 0) {
508 register_ioport_write(elcr_addr, 1, 1, elcr_ioport_write, s);
509 register_ioport_read(elcr_addr, 1, 1, elcr_ioport_read, s);
511 register_savevm("i8259", io_addr, 1, pic_save, pic_load, s);
512 qemu_register_reset(pic_reset, s);
524 s = &isa_pic->pics[i];
525 term_printf("pic%d: irr=%02x imr=%02x isr=%02x hprio=%d irq_base=%02x rr_sel=%d elcr=%02x fnm=%d\n",
526 i, s->irr, s->imr, s->isr, s->priority_add,
527 s->irq_base, s->read_reg_select, s->elcr,
528 s->special_fully_nested_mode);
534 #ifndef DEBUG_IRQ_COUNT
535 term_printf("irq statistic code not compiled.\n");
540 term_printf("IRQ statistics:\n");
541 for (i = 0; i < 16; i++) {
542 count = irq_count[i];
544 term_printf("%2d: %" PRId64 "\n", i, count);
549 PicState2 *pic_init(IRQRequestFunc *irq_request, void *irq_request_opaque)
552 s = qemu_mallocz(sizeof(PicState2));
555 pic_init1(0x20, 0x4d0, &s->pics[0]);
556 pic_init1(0xa0, 0x4d1, &s->pics[1]);
557 s->pics[0].elcr_mask = 0xf8;
558 s->pics[1].elcr_mask = 0xde;
559 s->irq_request = irq_request;
560 s->irq_request_opaque = irq_request_opaque;
561 s->pics[0].pics_state = s;
562 s->pics[1].pics_state = s;
566 void pic_set_alt_irq_func(PicState2 *s, SetIRQFunc *alt_irq_func,
567 void *alt_irq_opaque)
569 s->alt_irq_func = alt_irq_func;
570 s->alt_irq_opaque = alt_irq_opaque;