2 * QEMU 8259 interrupt controller emulation
4 * Copyright (c) 2003-2004 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
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29 //#define DEBUG_IRQ_LATENCY
31 typedef struct PicState {
32 uint8_t last_irr; /* edge detection */
33 uint8_t irr; /* interrupt request register */
34 uint8_t imr; /* interrupt mask register */
35 uint8_t isr; /* interrupt service register */
36 uint8_t priority_add; /* highest irq priority */
38 uint8_t read_reg_select;
43 uint8_t rotate_on_auto_eoi;
44 uint8_t special_fully_nested_mode;
45 uint8_t init4; /* true if 4 byte init */
46 uint8_t elcr; /* PIIX edge/trigger selection*/
50 /* 0 is master pic, 1 is slave pic */
51 static PicState pics[2];
52 static int pic_irq_requested;
54 /* set irq level. If an edge is detected, then the IRR is set to 1 */
55 static inline void pic_set_irq1(PicState *s, int irq, int level)
71 if ((s->last_irr & mask) == 0)
80 /* return the highest priority found in mask (highest = smallest
81 number). Return 8 if no irq */
82 static inline int get_priority(PicState *s, int mask)
88 while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0)
93 /* return the pic wanted interrupt. return -1 if none */
94 static int pic_get_irq(PicState *s)
96 int mask, cur_priority, priority;
98 mask = s->irr & ~s->imr;
99 priority = get_priority(s, mask);
102 /* compute current priority. If special fully nested mode on the
103 master, the IRQ coming from the slave is not taken into account
104 for the priority computation. */
106 if (s->special_fully_nested_mode && s == &pics[0])
108 cur_priority = get_priority(s, mask);
109 if (priority < cur_priority) {
110 /* higher priority found: an irq should be generated */
111 return (priority + s->priority_add) & 7;
117 /* raise irq to CPU if necessary. must be called every time the active
119 static void pic_update_irq(void)
123 /* first look at slave pic */
124 irq2 = pic_get_irq(&pics[1]);
126 /* if irq request by slave pic, signal master PIC */
127 pic_set_irq1(&pics[0], 2, 1);
128 pic_set_irq1(&pics[0], 2, 0);
130 /* look at requested irq */
131 irq = pic_get_irq(&pics[0]);
135 pic_irq_requested = 8 + irq2;
137 /* from master pic */
138 pic_irq_requested = irq;
140 #if defined(DEBUG_PIC)
143 for(i = 0; i < 2; i++) {
144 printf("pic%d: imr=%x irr=%x padd=%d\n",
145 i, pics[i].imr, pics[i].irr, pics[i].priority_add);
149 printf("pic: cpu_interrupt req=%d\n", pic_irq_requested);
151 cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HARD);
155 #ifdef DEBUG_IRQ_LATENCY
156 int64_t irq_time[16];
158 #if defined(DEBUG_PIC)
162 void pic_set_irq(int irq, int level)
164 #if defined(DEBUG_PIC)
165 if (level != irq_level[irq]) {
166 printf("pic_set_irq: irq=%d level=%d\n", irq, level);
167 irq_level[irq] = level;
170 #ifdef DEBUG_IRQ_LATENCY
172 irq_time[irq] = cpu_get_ticks();
175 pic_set_irq1(&pics[irq >> 3], irq & 7, level);
179 /* acknowledge interrupt 'irq' */
180 static inline void pic_intack(PicState *s, int irq)
183 if (s->rotate_on_auto_eoi)
184 s->priority_add = (irq + 1) & 7;
186 s->isr |= (1 << irq);
188 s->irr &= ~(1 << irq);
191 int cpu_get_pic_interrupt(CPUState *env)
193 int irq, irq2, intno;
195 /* signal the pic that the irq was acked by the CPU */
196 irq = pic_irq_requested;
197 #ifdef DEBUG_IRQ_LATENCY
198 printf("IRQ%d latency=%0.3fus\n",
200 (double)(cpu_get_ticks() - irq_time[irq]) * 1000000.0 / ticks_per_sec);
202 #if defined(DEBUG_PIC)
203 printf("pic_interrupt: irq=%d\n", irq);
208 pic_intack(&pics[1], irq2);
210 intno = pics[1].irq_base + irq2;
212 intno = pics[0].irq_base + irq;
214 pic_intack(&pics[0], irq);
219 static void pic_ioport_write(void *opaque, uint32_t addr, uint32_t val)
221 PicState *s = opaque;
222 int priority, cmd, irq, tmp;
225 printf("pic_write: addr=0x%02x val=0x%02x\n", addr, val);
232 memset(s, 0, sizeof(PicState));
238 hw_error("single mode not supported");
240 hw_error("level sensitive irq not supported");
241 } else if (val & 0x08) {
245 s->read_reg_select = val & 1;
247 s->special_mask = (val >> 5) & 1;
253 s->rotate_on_auto_eoi = cmd >> 2;
255 case 1: /* end of interrupt */
257 priority = get_priority(s, s->isr);
259 irq = (priority + s->priority_add) & 7;
260 s->isr &= ~(1 << irq);
262 s->priority_add = (irq + 1) & 7;
268 s->isr &= ~(1 << irq);
272 s->priority_add = (val + 1) & 7;
277 s->isr &= ~(1 << irq);
278 s->priority_add = (irq + 1) & 7;
287 switch(s->init_state) {
294 s->irq_base = val & 0xf8;
305 s->special_fully_nested_mode = (val >> 4) & 1;
306 s->auto_eoi = (val >> 1) & 1;
313 static uint32_t pic_poll_read (PicState *s, uint32_t addr1)
317 ret = pic_get_irq(s);
320 pics[0].isr &= ~(1 << 2);
321 pics[0].irr &= ~(1 << 2);
323 s->irr &= ~(1 << ret);
324 s->isr &= ~(1 << ret);
325 if (addr1 >> 7 || ret != 2)
335 static uint32_t pic_ioport_read(void *opaque, uint32_t addr1)
337 PicState *s = opaque;
344 ret = pic_poll_read(s, addr1);
348 if (s->read_reg_select)
357 printf("pic_read: addr=0x%02x val=0x%02x\n", addr1, ret);
362 /* memory mapped interrupt status */
363 uint32_t pic_intack_read(CPUState *env)
367 ret = pic_poll_read(&pics[0], 0x00);
369 ret = pic_poll_read(&pics[1], 0x80) + 8;
370 /* Prepare for ISR read */
371 pics[0].read_reg_select = 1;
376 static void elcr_ioport_write(void *opaque, uint32_t addr, uint32_t val)
378 PicState *s = opaque;
379 s->elcr = val & s->elcr_mask;
382 static uint32_t elcr_ioport_read(void *opaque, uint32_t addr1)
384 PicState *s = opaque;
388 static void pic_save(QEMUFile *f, void *opaque)
390 PicState *s = opaque;
392 qemu_put_8s(f, &s->last_irr);
393 qemu_put_8s(f, &s->irr);
394 qemu_put_8s(f, &s->imr);
395 qemu_put_8s(f, &s->isr);
396 qemu_put_8s(f, &s->priority_add);
397 qemu_put_8s(f, &s->irq_base);
398 qemu_put_8s(f, &s->read_reg_select);
399 qemu_put_8s(f, &s->poll);
400 qemu_put_8s(f, &s->special_mask);
401 qemu_put_8s(f, &s->init_state);
402 qemu_put_8s(f, &s->auto_eoi);
403 qemu_put_8s(f, &s->rotate_on_auto_eoi);
404 qemu_put_8s(f, &s->special_fully_nested_mode);
405 qemu_put_8s(f, &s->init4);
406 qemu_put_8s(f, &s->elcr);
409 static int pic_load(QEMUFile *f, void *opaque, int version_id)
411 PicState *s = opaque;
416 qemu_get_8s(f, &s->last_irr);
417 qemu_get_8s(f, &s->irr);
418 qemu_get_8s(f, &s->imr);
419 qemu_get_8s(f, &s->isr);
420 qemu_get_8s(f, &s->priority_add);
421 qemu_get_8s(f, &s->irq_base);
422 qemu_get_8s(f, &s->read_reg_select);
423 qemu_get_8s(f, &s->poll);
424 qemu_get_8s(f, &s->special_mask);
425 qemu_get_8s(f, &s->init_state);
426 qemu_get_8s(f, &s->auto_eoi);
427 qemu_get_8s(f, &s->rotate_on_auto_eoi);
428 qemu_get_8s(f, &s->special_fully_nested_mode);
429 qemu_get_8s(f, &s->init4);
430 qemu_get_8s(f, &s->elcr);
434 /* XXX: add generic master/slave system */
435 static void pic_init1(int io_addr, int elcr_addr, PicState *s)
437 register_ioport_write(io_addr, 2, 1, pic_ioport_write, s);
438 register_ioport_read(io_addr, 2, 1, pic_ioport_read, s);
439 if (elcr_addr >= 0) {
440 register_ioport_write(elcr_addr, 1, 1, elcr_ioport_write, s);
441 register_ioport_read(elcr_addr, 1, 1, elcr_ioport_read, s);
443 register_savevm("i8259", io_addr, 1, pic_save, pic_load, s);
453 term_printf("pic%d: irr=%02x imr=%02x isr=%02x hprio=%d irq_base=%02x rr_sel=%d elcr=%02x\n",
454 i, s->irr, s->imr, s->isr, s->priority_add,
455 s->irq_base, s->read_reg_select, s->elcr);
462 pic_init1(0x20, 0x4d0, &pics[0]);
463 pic_init1(0xa0, 0x4d1, &pics[1]);
464 pics[0].elcr_mask = 0xf8;
465 pics[1].elcr_mask = 0xde;