2 * QEMU 8259 interrupt controller emulation
4 * Copyright (c) 2003-2004 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
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29 //#define DEBUG_IRQ_LATENCY
31 typedef struct PicState {
32 uint8_t last_irr; /* edge detection */
33 uint8_t irr; /* interrupt request register */
34 uint8_t imr; /* interrupt mask register */
35 uint8_t isr; /* interrupt service register */
36 uint8_t priority_add; /* highest irq priority */
38 uint8_t read_reg_select;
43 uint8_t rotate_on_auto_eoi;
44 uint8_t special_fully_nested_mode;
45 uint8_t init4; /* true if 4 byte init */
48 /* 0 is master pic, 1 is slave pic */
50 int pic_irq_requested;
52 /* set irq level. If an edge is detected, then the IRR is set to 1 */
53 static inline void pic_set_irq1(PicState *s, int irq, int level)
58 if ((s->last_irr & mask) == 0)
66 /* return the highest priority found in mask (highest = smallest
67 number). Return 8 if no irq */
68 static inline int get_priority(PicState *s, int mask)
74 while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0)
79 /* return the pic wanted interrupt. return -1 if none */
80 static int pic_get_irq(PicState *s)
82 int mask, cur_priority, priority;
84 mask = s->irr & ~s->imr;
85 priority = get_priority(s, mask);
88 /* compute current priority. If special fully nested mode on the
89 master, the IRQ coming from the slave is not taken into account
90 for the priority computation. */
92 if (s->special_fully_nested_mode && s == &pics[0])
94 cur_priority = get_priority(s, mask);
95 if (priority < cur_priority) {
96 /* higher priority found: an irq should be generated */
97 return (priority + s->priority_add) & 7;
103 /* raise irq to CPU if necessary. must be called every time the active
105 static void pic_update_irq(void)
109 /* first look at slave pic */
110 irq2 = pic_get_irq(&pics[1]);
112 /* if irq request by slave pic, signal master PIC */
113 pic_set_irq1(&pics[0], 2, 1);
114 pic_set_irq1(&pics[0], 2, 0);
116 /* look at requested irq */
117 irq = pic_get_irq(&pics[0]);
121 pic_irq_requested = 8 + irq2;
123 /* from master pic */
124 pic_irq_requested = irq;
126 #if defined(DEBUG_PIC)
129 for(i = 0; i < 2; i++) {
130 printf("pic%d: imr=%x irr=%x padd=%d\n",
131 i, pics[i].imr, pics[i].irr, pics[i].priority_add);
135 printf("pic: cpu_interrupt req=%d\n", pic_irq_requested);
137 cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HARD);
141 #ifdef DEBUG_IRQ_LATENCY
142 int64_t irq_time[16];
144 #if defined(DEBUG_PIC)
148 void pic_set_irq(int irq, int level)
150 #if defined(DEBUG_PIC)
151 if (level != irq_level[irq]) {
152 printf("pic_set_irq: irq=%d level=%d\n", irq, level);
153 irq_level[irq] = level;
156 #ifdef DEBUG_IRQ_LATENCY
158 irq_time[irq] = cpu_get_ticks();
161 pic_set_irq1(&pics[irq >> 3], irq & 7, level);
165 /* acknowledge interrupt 'irq' */
166 static inline void pic_intack(PicState *s, int irq)
169 if (s->rotate_on_auto_eoi)
170 s->priority_add = (irq + 1) & 7;
172 s->isr |= (1 << irq);
174 s->irr &= ~(1 << irq);
177 int cpu_x86_get_pic_interrupt(CPUState *env)
179 int irq, irq2, intno;
181 /* signal the pic that the irq was acked by the CPU */
182 irq = pic_irq_requested;
183 #ifdef DEBUG_IRQ_LATENCY
184 printf("IRQ%d latency=%0.3fus\n",
186 (double)(cpu_get_ticks() - irq_time[irq]) * 1000000.0 / ticks_per_sec);
188 #if defined(DEBUG_PIC)
189 printf("pic_interrupt: irq=%d\n", irq);
194 pic_intack(&pics[1], irq2);
196 intno = pics[1].irq_base + irq2;
198 intno = pics[0].irq_base + irq;
200 pic_intack(&pics[0], irq);
204 static void pic_ioport_write(void *opaque, uint32_t addr, uint32_t val)
206 PicState *s = opaque;
207 int priority, cmd, irq;
210 printf("pic_write: addr=0x%02x val=0x%02x\n", addr, val);
216 memset(s, 0, sizeof(PicState));
220 hw_error("single mode not supported");
222 hw_error("level sensitive irq not supported");
223 } else if (val & 0x08) {
227 s->read_reg_select = val & 1;
229 s->special_mask = (val >> 5) & 1;
235 s->rotate_on_auto_eoi = cmd >> 2;
237 case 1: /* end of interrupt */
239 priority = get_priority(s, s->isr);
241 irq = (priority + s->priority_add) & 7;
242 s->isr &= ~(1 << irq);
244 s->priority_add = (irq + 1) & 7;
250 s->isr &= ~(1 << irq);
254 s->priority_add = (val + 1) & 7;
259 s->isr &= ~(1 << irq);
260 s->priority_add = (irq + 1) & 7;
269 switch(s->init_state) {
276 s->irq_base = val & 0xf8;
287 s->special_fully_nested_mode = (val >> 4) & 1;
288 s->auto_eoi = (val >> 1) & 1;
295 static uint32_t pic_poll_read (PicState *s, uint32_t addr1)
299 ret = pic_get_irq(s);
302 pics[0].isr &= ~(1 << 2);
303 pics[0].irr &= ~(1 << 2);
305 s->irr &= ~(1 << ret);
306 s->isr &= ~(1 << ret);
307 if (addr1 >> 7 || ret != 2)
317 static uint32_t pic_ioport_read(void *opaque, uint32_t addr1)
319 PicState *s = opaque;
326 ret = pic_poll_read(s, addr1);
330 if (s->read_reg_select)
339 printf("pic_read: addr=0x%02x val=0x%02x\n", addr1, ret);
344 /* memory mapped interrupt status */
345 uint32_t pic_intack_read(CPUState *env)
349 ret = pic_poll_read(&pics[0], 0x00);
351 ret = pic_poll_read(&pics[1], 0x80) + 8;
352 /* Prepare for ISR read */
353 pics[0].read_reg_select = 1;
358 static void pic_save(QEMUFile *f, void *opaque)
360 PicState *s = opaque;
362 qemu_put_8s(f, &s->last_irr);
363 qemu_put_8s(f, &s->irr);
364 qemu_put_8s(f, &s->imr);
365 qemu_put_8s(f, &s->isr);
366 qemu_put_8s(f, &s->priority_add);
367 qemu_put_8s(f, &s->irq_base);
368 qemu_put_8s(f, &s->read_reg_select);
369 qemu_put_8s(f, &s->poll);
370 qemu_put_8s(f, &s->special_mask);
371 qemu_put_8s(f, &s->init_state);
372 qemu_put_8s(f, &s->auto_eoi);
373 qemu_put_8s(f, &s->rotate_on_auto_eoi);
374 qemu_put_8s(f, &s->special_fully_nested_mode);
375 qemu_put_8s(f, &s->init4);
378 static int pic_load(QEMUFile *f, void *opaque, int version_id)
380 PicState *s = opaque;
385 qemu_get_8s(f, &s->last_irr);
386 qemu_get_8s(f, &s->irr);
387 qemu_get_8s(f, &s->imr);
388 qemu_get_8s(f, &s->isr);
389 qemu_get_8s(f, &s->priority_add);
390 qemu_get_8s(f, &s->irq_base);
391 qemu_get_8s(f, &s->read_reg_select);
392 qemu_get_8s(f, &s->poll);
393 qemu_get_8s(f, &s->special_mask);
394 qemu_get_8s(f, &s->init_state);
395 qemu_get_8s(f, &s->auto_eoi);
396 qemu_get_8s(f, &s->rotate_on_auto_eoi);
397 qemu_get_8s(f, &s->special_fully_nested_mode);
398 qemu_get_8s(f, &s->init4);
402 /* XXX: add generic master/slave system */
403 static void pic_init1(int io_addr, PicState *s)
405 register_ioport_write(io_addr, 2, 1, pic_ioport_write, s);
406 register_ioport_read(io_addr, 2, 1, pic_ioport_read, s);
408 register_savevm("i8259", io_addr, 1, pic_save, pic_load, s);
413 pic_init1(0x20, &pics[0]);
414 pic_init1(0xa0, &pics[1]);