2 * QEMU 8259 interrupt controller emulation
4 * Copyright (c) 2003-2004 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
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11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
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16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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29 //#define DEBUG_IRQ_LATENCY
31 typedef struct PicState {
32 uint8_t last_irr; /* edge detection */
33 uint8_t irr; /* interrupt request register */
34 uint8_t imr; /* interrupt mask register */
35 uint8_t isr; /* interrupt service register */
36 uint8_t priority_add; /* highest irq priority */
38 uint8_t read_reg_select;
43 uint8_t rotate_on_auto_eoi;
44 uint8_t special_fully_nested_mode;
45 uint8_t init4; /* true if 4 byte init */
46 uint8_t elcr; /* PIIX edge/trigger selection*/
50 /* 0 is master pic, 1 is slave pic */
51 static PicState pics[2];
53 /* set irq level. If an edge is detected, then the IRR is set to 1 */
54 static inline void pic_set_irq1(PicState *s, int irq, int level)
70 if ((s->last_irr & mask) == 0)
79 /* return the highest priority found in mask (highest = smallest
80 number). Return 8 if no irq */
81 static inline int get_priority(PicState *s, int mask)
87 while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0)
92 /* return the pic wanted interrupt. return -1 if none */
93 static int pic_get_irq(PicState *s)
95 int mask, cur_priority, priority;
97 mask = s->irr & ~s->imr;
98 priority = get_priority(s, mask);
101 /* compute current priority. If special fully nested mode on the
102 master, the IRQ coming from the slave is not taken into account
103 for the priority computation. */
105 if (s->special_fully_nested_mode && s == &pics[0])
107 cur_priority = get_priority(s, mask);
108 if (priority < cur_priority) {
109 /* higher priority found: an irq should be generated */
110 return (priority + s->priority_add) & 7;
116 /* raise irq to CPU if necessary. must be called every time the active
118 static void pic_update_irq(void)
122 /* first look at slave pic */
123 irq2 = pic_get_irq(&pics[1]);
125 /* if irq request by slave pic, signal master PIC */
126 pic_set_irq1(&pics[0], 2, 1);
127 pic_set_irq1(&pics[0], 2, 0);
129 /* look at requested irq */
130 irq = pic_get_irq(&pics[0]);
132 #if defined(DEBUG_PIC)
135 for(i = 0; i < 2; i++) {
136 printf("pic%d: imr=%x irr=%x padd=%d\n",
137 i, pics[i].imr, pics[i].irr, pics[i].priority_add);
141 printf("pic: cpu_interrupt req=%d\n", pic_irq_requested);
143 cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HARD);
147 #ifdef DEBUG_IRQ_LATENCY
148 int64_t irq_time[16];
150 #if defined(DEBUG_PIC)
154 void pic_set_irq(int irq, int level)
156 #if defined(DEBUG_PIC)
157 if (level != irq_level[irq]) {
158 printf("pic_set_irq: irq=%d level=%d\n", irq, level);
159 irq_level[irq] = level;
162 #ifdef DEBUG_IRQ_LATENCY
164 irq_time[irq] = cpu_get_ticks();
167 pic_set_irq1(&pics[irq >> 3], irq & 7, level);
171 /* acknowledge interrupt 'irq' */
172 static inline void pic_intack(PicState *s, int irq)
175 if (s->rotate_on_auto_eoi)
176 s->priority_add = (irq + 1) & 7;
178 s->isr |= (1 << irq);
180 s->irr &= ~(1 << irq);
183 int cpu_get_pic_interrupt(CPUState *env)
185 int irq, irq2, intno;
187 /* read the irq from the PIC */
189 irq = pic_get_irq(&pics[0]);
191 pic_intack(&pics[0], irq);
193 irq2 = pic_get_irq(&pics[1]);
195 pic_intack(&pics[1], irq2);
197 /* spurious IRQ on slave controller */
200 intno = pics[1].irq_base + irq2;
203 intno = pics[0].irq_base + irq;
206 /* spurious IRQ on host controller */
208 intno = pics[0].irq_base + irq;
212 #ifdef DEBUG_IRQ_LATENCY
213 printf("IRQ%d latency=%0.3fus\n",
215 (double)(cpu_get_ticks() - irq_time[irq]) * 1000000.0 / ticks_per_sec);
217 #if defined(DEBUG_PIC)
218 printf("pic_interrupt: irq=%d\n", irq);
223 static void pic_ioport_write(void *opaque, uint32_t addr, uint32_t val)
225 PicState *s = opaque;
226 int priority, cmd, irq, tmp;
229 printf("pic_write: addr=0x%02x val=0x%02x\n", addr, val);
236 memset(s, 0, sizeof(PicState));
238 /* deassert a pending interrupt */
239 cpu_reset_interrupt(cpu_single_env, CPU_INTERRUPT_HARD);
244 hw_error("single mode not supported");
246 hw_error("level sensitive irq not supported");
247 } else if (val & 0x08) {
251 s->read_reg_select = val & 1;
253 s->special_mask = (val >> 5) & 1;
259 s->rotate_on_auto_eoi = cmd >> 2;
261 case 1: /* end of interrupt */
263 priority = get_priority(s, s->isr);
265 irq = (priority + s->priority_add) & 7;
266 s->isr &= ~(1 << irq);
268 s->priority_add = (irq + 1) & 7;
274 s->isr &= ~(1 << irq);
278 s->priority_add = (val + 1) & 7;
283 s->isr &= ~(1 << irq);
284 s->priority_add = (irq + 1) & 7;
293 switch(s->init_state) {
300 s->irq_base = val & 0xf8;
311 s->special_fully_nested_mode = (val >> 4) & 1;
312 s->auto_eoi = (val >> 1) & 1;
319 static uint32_t pic_poll_read (PicState *s, uint32_t addr1)
323 ret = pic_get_irq(s);
326 pics[0].isr &= ~(1 << 2);
327 pics[0].irr &= ~(1 << 2);
329 s->irr &= ~(1 << ret);
330 s->isr &= ~(1 << ret);
331 if (addr1 >> 7 || ret != 2)
341 static uint32_t pic_ioport_read(void *opaque, uint32_t addr1)
343 PicState *s = opaque;
350 ret = pic_poll_read(s, addr1);
354 if (s->read_reg_select)
363 printf("pic_read: addr=0x%02x val=0x%02x\n", addr1, ret);
368 /* memory mapped interrupt status */
369 uint32_t pic_intack_read(CPUState *env)
373 ret = pic_poll_read(&pics[0], 0x00);
375 ret = pic_poll_read(&pics[1], 0x80) + 8;
376 /* Prepare for ISR read */
377 pics[0].read_reg_select = 1;
382 static void elcr_ioport_write(void *opaque, uint32_t addr, uint32_t val)
384 PicState *s = opaque;
385 s->elcr = val & s->elcr_mask;
388 static uint32_t elcr_ioport_read(void *opaque, uint32_t addr1)
390 PicState *s = opaque;
394 static void pic_save(QEMUFile *f, void *opaque)
396 PicState *s = opaque;
398 qemu_put_8s(f, &s->last_irr);
399 qemu_put_8s(f, &s->irr);
400 qemu_put_8s(f, &s->imr);
401 qemu_put_8s(f, &s->isr);
402 qemu_put_8s(f, &s->priority_add);
403 qemu_put_8s(f, &s->irq_base);
404 qemu_put_8s(f, &s->read_reg_select);
405 qemu_put_8s(f, &s->poll);
406 qemu_put_8s(f, &s->special_mask);
407 qemu_put_8s(f, &s->init_state);
408 qemu_put_8s(f, &s->auto_eoi);
409 qemu_put_8s(f, &s->rotate_on_auto_eoi);
410 qemu_put_8s(f, &s->special_fully_nested_mode);
411 qemu_put_8s(f, &s->init4);
412 qemu_put_8s(f, &s->elcr);
415 static int pic_load(QEMUFile *f, void *opaque, int version_id)
417 PicState *s = opaque;
422 qemu_get_8s(f, &s->last_irr);
423 qemu_get_8s(f, &s->irr);
424 qemu_get_8s(f, &s->imr);
425 qemu_get_8s(f, &s->isr);
426 qemu_get_8s(f, &s->priority_add);
427 qemu_get_8s(f, &s->irq_base);
428 qemu_get_8s(f, &s->read_reg_select);
429 qemu_get_8s(f, &s->poll);
430 qemu_get_8s(f, &s->special_mask);
431 qemu_get_8s(f, &s->init_state);
432 qemu_get_8s(f, &s->auto_eoi);
433 qemu_get_8s(f, &s->rotate_on_auto_eoi);
434 qemu_get_8s(f, &s->special_fully_nested_mode);
435 qemu_get_8s(f, &s->init4);
436 qemu_get_8s(f, &s->elcr);
440 /* XXX: add generic master/slave system */
441 static void pic_init1(int io_addr, int elcr_addr, PicState *s)
443 register_ioport_write(io_addr, 2, 1, pic_ioport_write, s);
444 register_ioport_read(io_addr, 2, 1, pic_ioport_read, s);
445 if (elcr_addr >= 0) {
446 register_ioport_write(elcr_addr, 1, 1, elcr_ioport_write, s);
447 register_ioport_read(elcr_addr, 1, 1, elcr_ioport_read, s);
449 register_savevm("i8259", io_addr, 1, pic_save, pic_load, s);
459 term_printf("pic%d: irr=%02x imr=%02x isr=%02x hprio=%d irq_base=%02x rr_sel=%d elcr=%02x fnm=%d\n",
460 i, s->irr, s->imr, s->isr, s->priority_add,
461 s->irq_base, s->read_reg_select, s->elcr,
462 s->special_fully_nested_mode);
469 pic_init1(0x20, 0x4d0, &pics[0]);
470 pic_init1(0xa0, 0x4d1, &pics[1]);
471 pics[0].elcr_mask = 0xf8;
472 pics[1].elcr_mask = 0xde;