2 * QEMU 8259 interrupt controller emulation
4 * Copyright (c) 2003-2004 Fabrice Bellard
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29 //#define DEBUG_IRQ_LATENCY
30 //#define DEBUG_IRQ_COUNT
32 typedef struct PicState {
33 uint8_t last_irr; /* edge detection */
34 uint8_t irr; /* interrupt request register */
35 uint8_t imr; /* interrupt mask register */
36 uint8_t isr; /* interrupt service register */
37 uint8_t priority_add; /* highest irq priority */
39 uint8_t read_reg_select;
44 uint8_t rotate_on_auto_eoi;
45 uint8_t special_fully_nested_mode;
46 uint8_t init4; /* true if 4 byte init */
47 uint8_t elcr; /* PIIX edge/trigger selection*/
51 /* 0 is master pic, 1 is slave pic */
52 static PicState pics[2];
54 #if defined(DEBUG_PIC) || defined (DEBUG_IRQ_COUNT)
55 static int irq_level[16];
57 #ifdef DEBUG_IRQ_COUNT
58 static uint64_t irq_count[16];
61 /* set irq level. If an edge is detected, then the IRR is set to 1 */
62 static inline void pic_set_irq1(PicState *s, int irq, int level)
78 if ((s->last_irr & mask) == 0)
87 /* return the highest priority found in mask (highest = smallest
88 number). Return 8 if no irq */
89 static inline int get_priority(PicState *s, int mask)
95 while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0)
100 /* return the pic wanted interrupt. return -1 if none */
101 static int pic_get_irq(PicState *s)
103 int mask, cur_priority, priority;
105 mask = s->irr & ~s->imr;
106 priority = get_priority(s, mask);
109 /* compute current priority. If special fully nested mode on the
110 master, the IRQ coming from the slave is not taken into account
111 for the priority computation. */
113 if (s->special_fully_nested_mode && s == &pics[0])
115 cur_priority = get_priority(s, mask);
116 if (priority < cur_priority) {
117 /* higher priority found: an irq should be generated */
118 return (priority + s->priority_add) & 7;
124 /* raise irq to CPU if necessary. must be called every time the active
126 static void pic_update_irq(void)
130 /* first look at slave pic */
131 irq2 = pic_get_irq(&pics[1]);
133 /* if irq request by slave pic, signal master PIC */
134 pic_set_irq1(&pics[0], 2, 1);
135 pic_set_irq1(&pics[0], 2, 0);
137 /* look at requested irq */
138 irq = pic_get_irq(&pics[0]);
140 #if defined(DEBUG_PIC)
143 for(i = 0; i < 2; i++) {
144 printf("pic%d: imr=%x irr=%x padd=%d\n",
145 i, pics[i].imr, pics[i].irr, pics[i].priority_add);
149 printf("pic: cpu_interrupt\n");
151 cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HARD);
155 #ifdef DEBUG_IRQ_LATENCY
156 int64_t irq_time[16];
159 void pic_set_irq(int irq, int level)
161 #if defined(DEBUG_PIC) || defined(DEBUG_IRQ_COUNT)
162 if (level != irq_level[irq]) {
163 #if defined(DEBUG_PIC)
164 printf("pic_set_irq: irq=%d level=%d\n", irq, level);
166 irq_level[irq] = level;
167 #ifdef DEBUG_IRQ_COUNT
173 #ifdef DEBUG_IRQ_LATENCY
175 irq_time[irq] = qemu_get_clock(vm_clock);
178 pic_set_irq1(&pics[irq >> 3], irq & 7, level);
182 /* acknowledge interrupt 'irq' */
183 static inline void pic_intack(PicState *s, int irq)
186 if (s->rotate_on_auto_eoi)
187 s->priority_add = (irq + 1) & 7;
189 s->isr |= (1 << irq);
191 /* We don't clear a level sensitive interrupt here */
192 if (!(s->elcr & (1 << irq)))
193 s->irr &= ~(1 << irq);
196 int cpu_get_pic_interrupt(CPUState *env)
198 int irq, irq2, intno;
200 /* read the irq from the PIC */
202 irq = pic_get_irq(&pics[0]);
204 pic_intack(&pics[0], irq);
206 irq2 = pic_get_irq(&pics[1]);
208 pic_intack(&pics[1], irq2);
210 /* spurious IRQ on slave controller */
213 intno = pics[1].irq_base + irq2;
216 intno = pics[0].irq_base + irq;
219 /* spurious IRQ on host controller */
221 intno = pics[0].irq_base + irq;
225 #ifdef DEBUG_IRQ_LATENCY
226 printf("IRQ%d latency=%0.3fus\n",
228 (double)(qemu_get_clock(vm_clock) - irq_time[irq]) * 1000000.0 / ticks_per_sec);
230 #if defined(DEBUG_PIC)
231 printf("pic_interrupt: irq=%d\n", irq);
236 static void pic_reset(void *opaque)
238 PicState *s = opaque;
242 memset(s, 0, sizeof(PicState));
246 static void pic_ioport_write(void *opaque, uint32_t addr, uint32_t val)
248 PicState *s = opaque;
249 int priority, cmd, irq;
252 printf("pic_write: addr=0x%02x val=0x%02x\n", addr, val);
259 /* deassert a pending interrupt */
260 cpu_reset_interrupt(cpu_single_env, CPU_INTERRUPT_HARD);
265 hw_error("single mode not supported");
267 hw_error("level sensitive irq not supported");
268 } else if (val & 0x08) {
272 s->read_reg_select = val & 1;
274 s->special_mask = (val >> 5) & 1;
280 s->rotate_on_auto_eoi = cmd >> 2;
282 case 1: /* end of interrupt */
284 priority = get_priority(s, s->isr);
286 irq = (priority + s->priority_add) & 7;
287 s->isr &= ~(1 << irq);
289 s->priority_add = (irq + 1) & 7;
295 s->isr &= ~(1 << irq);
299 s->priority_add = (val + 1) & 7;
304 s->isr &= ~(1 << irq);
305 s->priority_add = (irq + 1) & 7;
314 switch(s->init_state) {
321 s->irq_base = val & 0xf8;
332 s->special_fully_nested_mode = (val >> 4) & 1;
333 s->auto_eoi = (val >> 1) & 1;
340 static uint32_t pic_poll_read (PicState *s, uint32_t addr1)
344 ret = pic_get_irq(s);
347 pics[0].isr &= ~(1 << 2);
348 pics[0].irr &= ~(1 << 2);
350 s->irr &= ~(1 << ret);
351 s->isr &= ~(1 << ret);
352 if (addr1 >> 7 || ret != 2)
362 static uint32_t pic_ioport_read(void *opaque, uint32_t addr1)
364 PicState *s = opaque;
371 ret = pic_poll_read(s, addr1);
375 if (s->read_reg_select)
384 printf("pic_read: addr=0x%02x val=0x%02x\n", addr1, ret);
389 /* memory mapped interrupt status */
390 uint32_t pic_intack_read(CPUState *env)
394 ret = pic_poll_read(&pics[0], 0x00);
396 ret = pic_poll_read(&pics[1], 0x80) + 8;
397 /* Prepare for ISR read */
398 pics[0].read_reg_select = 1;
403 static void elcr_ioport_write(void *opaque, uint32_t addr, uint32_t val)
405 PicState *s = opaque;
406 s->elcr = val & s->elcr_mask;
409 static uint32_t elcr_ioport_read(void *opaque, uint32_t addr1)
411 PicState *s = opaque;
415 static void pic_save(QEMUFile *f, void *opaque)
417 PicState *s = opaque;
419 qemu_put_8s(f, &s->last_irr);
420 qemu_put_8s(f, &s->irr);
421 qemu_put_8s(f, &s->imr);
422 qemu_put_8s(f, &s->isr);
423 qemu_put_8s(f, &s->priority_add);
424 qemu_put_8s(f, &s->irq_base);
425 qemu_put_8s(f, &s->read_reg_select);
426 qemu_put_8s(f, &s->poll);
427 qemu_put_8s(f, &s->special_mask);
428 qemu_put_8s(f, &s->init_state);
429 qemu_put_8s(f, &s->auto_eoi);
430 qemu_put_8s(f, &s->rotate_on_auto_eoi);
431 qemu_put_8s(f, &s->special_fully_nested_mode);
432 qemu_put_8s(f, &s->init4);
433 qemu_put_8s(f, &s->elcr);
436 static int pic_load(QEMUFile *f, void *opaque, int version_id)
438 PicState *s = opaque;
443 qemu_get_8s(f, &s->last_irr);
444 qemu_get_8s(f, &s->irr);
445 qemu_get_8s(f, &s->imr);
446 qemu_get_8s(f, &s->isr);
447 qemu_get_8s(f, &s->priority_add);
448 qemu_get_8s(f, &s->irq_base);
449 qemu_get_8s(f, &s->read_reg_select);
450 qemu_get_8s(f, &s->poll);
451 qemu_get_8s(f, &s->special_mask);
452 qemu_get_8s(f, &s->init_state);
453 qemu_get_8s(f, &s->auto_eoi);
454 qemu_get_8s(f, &s->rotate_on_auto_eoi);
455 qemu_get_8s(f, &s->special_fully_nested_mode);
456 qemu_get_8s(f, &s->init4);
457 qemu_get_8s(f, &s->elcr);
461 /* XXX: add generic master/slave system */
462 static void pic_init1(int io_addr, int elcr_addr, PicState *s)
464 register_ioport_write(io_addr, 2, 1, pic_ioport_write, s);
465 register_ioport_read(io_addr, 2, 1, pic_ioport_read, s);
466 if (elcr_addr >= 0) {
467 register_ioport_write(elcr_addr, 1, 1, elcr_ioport_write, s);
468 register_ioport_read(elcr_addr, 1, 1, elcr_ioport_read, s);
470 register_savevm("i8259", io_addr, 1, pic_save, pic_load, s);
471 qemu_register_reset(pic_reset, s);
481 term_printf("pic%d: irr=%02x imr=%02x isr=%02x hprio=%d irq_base=%02x rr_sel=%d elcr=%02x fnm=%d\n",
482 i, s->irr, s->imr, s->isr, s->priority_add,
483 s->irq_base, s->read_reg_select, s->elcr,
484 s->special_fully_nested_mode);
490 #ifndef DEBUG_IRQ_COUNT
491 term_printf("irq statistic code not compiled.\n");
496 term_printf("IRQ statistics:\n");
497 for (i = 0; i < 16; i++) {
498 count = irq_count[i];
500 term_printf("%2d: %lld\n", i, count);
507 pic_init1(0x20, 0x4d0, &pics[0]);
508 pic_init1(0xa0, 0x4d1, &pics[1]);
509 pics[0].elcr_mask = 0xf8;
510 pics[1].elcr_mask = 0xde;