2 * QEMU ETRAX System Emulator
4 * Copyright (c) 2007 Edgar E. Iglesias, Axis Communications AB.
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
28 void etrax_ack_irq(CPUState *env, uint32_t mask);
30 #define R_TIME 0xb001e038
31 #define RW_TMR0_DIV 0xb001e000
32 #define R_TMR0_DATA 0xb001e004
33 #define RW_TMR0_CTRL 0xb001e008
34 #define RW_TMR1_DIV 0xb001e010
35 #define R_TMR1_DATA 0xb001e014
36 #define RW_TMR1_CTRL 0xb001e018
38 #define RW_INTR_MASK 0xb001e048
39 #define RW_ACK_INTR 0xb001e04c
40 #define R_INTR 0xb001e050
41 #define R_MASKED_INTR 0xb001e054
44 uint32_t rw_intr_mask;
58 static struct fs_timer_t timer0;
60 /* diff two timevals. Return a single int in us. */
61 int diff_timeval_us(struct timeval *a, struct timeval *b)
65 /* assume these values are signed. */
66 diff = (a->tv_sec - b->tv_sec) * 1000 * 1000;
67 diff += (a->tv_usec - b->tv_usec);
71 static uint32_t timer_readb (void *opaque, target_phys_addr_t addr)
73 CPUState *env = opaque;
75 printf ("%s %x pc=%x\n", __func__, addr, env->pc);
78 static uint32_t timer_readw (void *opaque, target_phys_addr_t addr)
80 CPUState *env = opaque;
82 printf ("%s %x pc=%x\n", __func__, addr, env->pc);
86 static uint32_t timer_readl (void *opaque, target_phys_addr_t addr)
88 CPUState *env = opaque;
95 printf ("R_TMR1_DATA\n");
99 static struct timeval last;
101 gettimeofday(&now, NULL);
102 if (!(last.tv_sec == 0 && last.tv_usec == 0)) {
103 r = diff_timeval_us(&now, &last);
104 r *= 1000; /* convert to ns. */
105 r++; /* make sure we increase for each call. */
115 r = r_intr & rw_intr_mask;
118 printf ("%s %x p=%x\n", __func__, addr, env->pc);
125 timer_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)
127 CPUState *env = opaque;
128 printf ("%s %x %x pc=%x\n", __func__, addr, value, env->pc);
131 timer_writew (void *opaque, target_phys_addr_t addr, uint32_t value)
133 CPUState *env = opaque;
134 printf ("%s %x %x pc=%x\n", __func__, addr, value, env->pc);
137 static void write_ctrl(struct fs_timer_t *t, uint32_t v)
151 printf ("extern or disabled timer clock?\n");
153 case 4: freq_hz = 29493000; break;
154 case 5: freq_hz = 32000000; break;
155 case 6: freq_hz = 32768000; break;
156 case 7: freq_hz = 100000000; break;
162 printf ("freq_hz=%d limit=%d\n", freq_hz, t->limit);
167 ptimer_set_period(timer0.ptimer, freq_hz / t->scale);
170 printf ("op=%d\n", op);
174 printf ("limit=%d %d\n", t->limit, t->limit/t->scale);
175 ptimer_set_limit(t->ptimer, t->limit / t->scale, 1);
178 ptimer_stop(t->ptimer);
181 ptimer_run(t->ptimer, 0);
189 static void timer_ack_irq(void)
191 if (!(r_intr & timer0.mask & rw_intr_mask)) {
192 qemu_irq_lower(timer0.irq[0]);
193 etrax_ack_irq(timer0.env, 1 << 0x1b);
198 timer_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
200 CPUState *env = opaque;
201 printf ("%s %x %x pc=%x\n",
202 __func__, addr, value, env->pc);
206 printf ("RW_TMR0_DIV=%x\n", value);
207 timer0.limit = value;
210 printf ("RW_TMR0_CTRL=%x\n", value);
211 write_ctrl(&timer0, value);
214 printf ("RW_TMR1_DIV=%x\n", value);
217 printf ("RW_TMR1_CTRL=%x\n", value);
220 printf ("RW_INTR_MASK=%x\n", value);
221 rw_intr_mask = value;
228 printf ("%s %x %x pc=%x\n",
229 __func__, addr, value, env->pc);
234 static CPUReadMemoryFunc *timer_read[] = {
240 static CPUWriteMemoryFunc *timer_write[] = {
246 static void timer_irq(void *opaque)
248 struct fs_timer_t *t = opaque;
251 if (t->mask & rw_intr_mask) {
252 qemu_irq_raise(t->irq[0]);
256 void etraxfs_timer_init(CPUState *env, qemu_irq *irqs)
260 timer0.bh = qemu_bh_new(timer_irq, &timer0);
261 timer0.ptimer = ptimer_init(timer0.bh);
262 timer0.irq = irqs + 0x1b;
266 timer_regs = cpu_register_io_memory(0, timer_read, timer_write, env);
267 cpu_register_physical_memory (0xb001e000, 0x5c, timer_regs);