2 * QEMU ESP/NCR53C9x emulation
4 * Copyright (c) 2005-2006 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
30 * On Sparc32, this is the ESP (NCR53C90) part of chip STP2000 (Master I/O), also
31 * produced as NCR89C100. See
32 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt
34 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR53C9X.txt
38 #define DPRINTF(fmt, args...) \
39 do { printf("ESP: " fmt , ##args); } while (0)
41 #define DPRINTF(fmt, args...)
44 #define ESP_MAXREG 0x3f
47 typedef struct ESPState ESPState;
50 BlockDriverState **bd;
51 uint8_t rregs[ESP_MAXREG];
52 uint8_t wregs[ESP_MAXREG];
54 uint32_t ti_rptr, ti_wptr;
55 uint8_t ti_buf[TI_BUFSZ];
58 SCSIDevice *scsi_dev[MAX_DISKS];
59 SCSIDevice *current_dev;
60 uint8_t cmdbuf[TI_BUFSZ];
64 /* The amount of data left in the current DMA transfer. */
66 /* The size of the current DMA transfer. Zero if no transfer is in
94 static int get_cmd(ESPState *s, uint8_t *buf)
99 dmalen = s->rregs[0] | (s->rregs[1] << 8);
100 target = s->wregs[4] & 7;
101 DPRINTF("get_cmd: len %d target %d\n", dmalen, target);
103 espdma_memory_read(s->dma_opaque, buf, dmalen);
106 memcpy(&buf[1], s->ti_buf, dmalen);
114 if (s->current_dev) {
115 /* Started a new command before the old one finished. Cancel it. */
116 scsi_cancel_io(s->current_dev, 0);
120 if (target >= MAX_DISKS || !s->scsi_dev[target]) {
122 s->rregs[4] = STAT_IN;
123 s->rregs[5] = INTR_DC;
125 espdma_raise_irq(s->dma_opaque);
128 s->current_dev = s->scsi_dev[target];
132 static void do_cmd(ESPState *s, uint8_t *buf)
137 DPRINTF("do_cmd: busid 0x%x\n", buf[0]);
139 datalen = scsi_send_command(s->current_dev, 0, &buf[1], lun);
140 s->ti_size = datalen;
142 s->rregs[4] = STAT_IN | STAT_TC;
146 s->rregs[4] |= STAT_DI;
147 scsi_read_data(s->current_dev, 0);
149 s->rregs[4] |= STAT_DO;
150 scsi_write_data(s->current_dev, 0);
153 s->rregs[5] = INTR_BS | INTR_FC;
154 s->rregs[6] = SEQ_CD;
155 espdma_raise_irq(s->dma_opaque);
158 static void handle_satn(ESPState *s)
163 len = get_cmd(s, buf);
168 static void handle_satn_stop(ESPState *s)
170 s->cmdlen = get_cmd(s, s->cmdbuf);
172 DPRINTF("Set ATN & Stop: cmdlen %d\n", s->cmdlen);
174 s->rregs[4] = STAT_IN | STAT_TC | STAT_CD;
175 s->rregs[5] = INTR_BS | INTR_FC;
176 s->rregs[6] = SEQ_CD;
177 espdma_raise_irq(s->dma_opaque);
181 static void write_response(ESPState *s)
183 DPRINTF("Transfer status (sense=%d)\n", s->sense);
184 s->ti_buf[0] = s->sense;
187 espdma_memory_write(s->dma_opaque, s->ti_buf, 2);
188 s->rregs[4] = STAT_IN | STAT_TC | STAT_ST;
189 s->rregs[5] = INTR_BS | INTR_FC;
190 s->rregs[6] = SEQ_CD;
197 espdma_raise_irq(s->dma_opaque);
200 static void esp_dma_done(ESPState *s)
202 s->rregs[4] |= STAT_IN | STAT_TC;
203 s->rregs[5] = INTR_BS;
208 espdma_raise_irq(s->dma_opaque);
211 static void esp_do_dma(ESPState *s)
216 to_device = (s->ti_size < 0);
219 DPRINTF("command len %d + %d\n", s->cmdlen, len);
220 espdma_memory_read(s->dma_opaque, &s->cmdbuf[s->cmdlen], len);
224 do_cmd(s, s->cmdbuf);
227 if (s->async_len == 0) {
228 /* Defer until data is available. */
231 if (len > s->async_len) {
235 espdma_memory_read(s->dma_opaque, s->async_buf, len);
237 espdma_memory_write(s->dma_opaque, s->async_buf, len);
246 if (s->async_len == 0) {
248 // ti_size is negative
249 scsi_write_data(s->current_dev, 0);
251 scsi_read_data(s->current_dev, 0);
252 /* If there is still data to be read from the device then
253 complete the DMA operation immeriately. Otherwise defer
254 until the scsi layer has completed. */
255 if (s->dma_left == 0 && s->ti_size > 0) {
260 /* Partially filled a scsi buffer. Complete immediately. */
265 static void esp_command_complete(void *opaque, int reason, uint32_t tag,
268 ESPState *s = (ESPState *)opaque;
270 if (reason == SCSI_REASON_DONE) {
271 DPRINTF("SCSI Command complete\n");
273 DPRINTF("SCSI command completed unexpectedly\n");
278 DPRINTF("Command failed\n");
280 s->rregs[4] = STAT_ST;
282 s->current_dev = NULL;
284 DPRINTF("transfer %d/%d\n", s->dma_left, s->ti_size);
286 s->async_buf = scsi_get_buf(s->current_dev, 0);
289 } else if (s->dma_counter != 0 && s->ti_size <= 0) {
290 /* If this was the last part of a DMA transfer then the
291 completion interrupt is deferred to here. */
297 static void handle_ti(ESPState *s)
299 uint32_t dmalen, minlen;
301 dmalen = s->rregs[0] | (s->rregs[1] << 8);
305 s->dma_counter = dmalen;
308 minlen = (dmalen < 32) ? dmalen : 32;
309 else if (s->ti_size < 0)
310 minlen = (dmalen < -s->ti_size) ? dmalen : -s->ti_size;
312 minlen = (dmalen < s->ti_size) ? dmalen : s->ti_size;
313 DPRINTF("Transfer Information len %d\n", minlen);
315 s->dma_left = minlen;
316 s->rregs[4] &= ~STAT_TC;
318 } else if (s->do_cmd) {
319 DPRINTF("command len %d\n", s->cmdlen);
323 do_cmd(s, s->cmdbuf);
328 void esp_reset(void *opaque)
330 ESPState *s = opaque;
332 memset(s->rregs, 0, ESP_MAXREG);
333 memset(s->wregs, 0, ESP_MAXREG);
334 s->rregs[0x0e] = 0x4; // Indicate fas100a
342 static uint32_t esp_mem_readb(void *opaque, target_phys_addr_t addr)
344 ESPState *s = opaque;
347 saddr = (addr & ESP_MAXREG) >> 2;
348 DPRINTF("read reg[%d]: 0x%2.2x\n", saddr, s->rregs[saddr]);
352 if (s->ti_size > 0) {
354 if ((s->rregs[4] & 6) == 0) {
356 fprintf(stderr, "esp: PIO data read not implemented\n");
359 s->rregs[2] = s->ti_buf[s->ti_rptr++];
361 espdma_raise_irq(s->dma_opaque);
363 if (s->ti_size == 0) {
370 // Clear interrupt/error status bits
371 s->rregs[4] &= ~(STAT_IN | STAT_GE | STAT_PE);
372 espdma_clear_irq(s->dma_opaque);
377 return s->rregs[saddr];
380 static void esp_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
382 ESPState *s = opaque;
385 saddr = (addr & ESP_MAXREG) >> 2;
386 DPRINTF("write reg[%d]: 0x%2.2x -> 0x%2.2x\n", saddr, s->wregs[saddr], val);
390 s->rregs[4] &= ~STAT_TC;
395 s->cmdbuf[s->cmdlen++] = val & 0xff;
396 } else if ((s->rregs[4] & 6) == 0) {
400 fprintf(stderr, "esp: PIO data write not implemented\n");
403 s->ti_buf[s->ti_wptr++] = val & 0xff;
407 s->rregs[saddr] = val;
411 /* Reload DMA counter. */
412 s->rregs[0] = s->wregs[0];
413 s->rregs[1] = s->wregs[1];
419 DPRINTF("NOP (%2.2x)\n", val);
422 DPRINTF("Flush FIFO (%2.2x)\n", val);
424 s->rregs[5] = INTR_FC;
428 DPRINTF("Chip reset (%2.2x)\n", val);
432 DPRINTF("Bus reset (%2.2x)\n", val);
433 s->rregs[5] = INTR_RST;
434 if (!(s->wregs[8] & 0x40)) {
435 espdma_raise_irq(s->dma_opaque);
442 DPRINTF("Initiator Command Complete Sequence (%2.2x)\n", val);
446 DPRINTF("Message Accepted (%2.2x)\n", val);
448 s->rregs[5] = INTR_DC;
452 DPRINTF("Set ATN (%2.2x)\n", val);
455 DPRINTF("Set ATN (%2.2x)\n", val);
459 DPRINTF("Set ATN & stop (%2.2x)\n", val);
463 DPRINTF("Unhandled ESP command (%2.2x)\n", val);
470 s->rregs[saddr] = val;
475 s->rregs[saddr] = val & 0x15;
478 s->rregs[saddr] = val;
483 s->wregs[saddr] = val;
486 static CPUReadMemoryFunc *esp_mem_read[3] = {
492 static CPUWriteMemoryFunc *esp_mem_write[3] = {
498 static void esp_save(QEMUFile *f, void *opaque)
500 ESPState *s = opaque;
502 qemu_put_buffer(f, s->rregs, ESP_MAXREG);
503 qemu_put_buffer(f, s->wregs, ESP_MAXREG);
504 qemu_put_be32s(f, &s->ti_size);
505 qemu_put_be32s(f, &s->ti_rptr);
506 qemu_put_be32s(f, &s->ti_wptr);
507 qemu_put_buffer(f, s->ti_buf, TI_BUFSZ);
508 qemu_put_be32s(f, &s->dma);
511 static int esp_load(QEMUFile *f, void *opaque, int version_id)
513 ESPState *s = opaque;
516 return -EINVAL; // Cannot emulate 1
518 qemu_get_buffer(f, s->rregs, ESP_MAXREG);
519 qemu_get_buffer(f, s->wregs, ESP_MAXREG);
520 qemu_get_be32s(f, &s->ti_size);
521 qemu_get_be32s(f, &s->ti_rptr);
522 qemu_get_be32s(f, &s->ti_wptr);
523 qemu_get_buffer(f, s->ti_buf, TI_BUFSZ);
524 qemu_get_be32s(f, &s->dma);
529 void *esp_init(BlockDriverState **bd, uint32_t espaddr, void *dma_opaque)
535 s = qemu_mallocz(sizeof(ESPState));
540 s->dma_opaque = dma_opaque;
542 esp_io_memory = cpu_register_io_memory(0, esp_mem_read, esp_mem_write, s);
543 cpu_register_physical_memory(espaddr, ESP_MAXREG*4, esp_io_memory);
547 register_savevm("esp", espaddr, 2, esp_save, esp_load, s);
548 qemu_register_reset(esp_reset, s);
549 for (i = 0; i < MAX_DISKS; i++) {
551 /* Command queueing is not implemented. */
553 scsi_disk_init(bs_table[i], 0, esp_command_complete, s);